E.F. Crabbe

A silicon nanocrystals based memory

A new memory structure using threshold shifting from charge stored in nanocrystals of silicon (≊5nm in size) is described. The devices utilize direct tunneling and storage of electrons in the nanocrystals. The limited size and capacitance of the nanocrystals limit the numbers of stored electrons. Coulomb blockade effects may be important in these structures but are not necessary for their operation. The threshold shifts of 0.2–0.4 V with read and write times less than 100’s of a nanosecond at operating voltages below 2.5 V have been obtained experimentally. The retention times are measured in days and weeks, and the structures have been operated in an excess of 109 cycles without degradation in performance. This nanomemory exhibits characteristics necessary for high density and low power.

75-GHz f/sub T/ SiGe-base heterojunction bipolar transistors

The fabrication of silicon heterojunction bipolar transistors which have a record unity-current-gain cutoff frequency (f/sub T/) of 75 GHz for a collector-base bias of 1 V, an intrinsic base sheet resistance (R/sub bi/) of 17 k Omega / Square Operator , and an emitter width of 0.9 mu m is discussed. This performance level, which represents an increase by almost a factor of 2 in the speed of a Si bipolar transistor, was achieved in a poly-emitter bipolar process by using SiGe for the base material. The germanium was graded in the 45-nm base to create a drift field of approximately 20 kV/cm, resulting in an intrinsic transit time of only 1.9 ps.<<ETX>>

Si/SiGe epitaxial-base transistors. I. Materials, physics, and circuits

A detailed review of SiGe epitaxial base technology is presented, which chronicles the progression of research from materials deposition through device and integration demonstrations, culminating in the first SiGe integrated circuit application. In part I of this paper, the requirements and processes for high-quality SiGe film preparation are discussed, with emphasis on fundamental principles. A detailed overview of SiGe HBT device design and implications for circuit applications is then presented. >

SiGe-channel heterojunction p-MOSFET's

The advances in the growth of pseudomorphic silicon-germanium epitaxial layers combined with the strong need for high-speed complementary circuits have led to increased interest in silicon-based heterojunction field-effect transistors. Metal-oxide-semiconductor field-effect transistors (MOSFETs) with SiGe channels are guided by different design rules than state-of-the-art silicon MOSFETs. The selection of the transistor gate material, the optimization of the silicon-germanium channel profile, the method of threshold voltage adjustment, and the silicon-cap and gate-oxide thickness sensitivities are the critical design parameters for the p-channel SiGe MOSFET. Two-dimensional numerical modeling demonstrates that n/sup +/ polysilicon-gate SiGe p-MOSFETs have acceptable short-channel behavior at 0.20 /spl mu/m channel lengths and are preferable to p/sup +/ polysilicon-gate p-MOSFETs for 2.5 V operation. Experimental results of n/sup +/-gate modulation-doped SiGe p-MOSFETs illustrate the importance of the optimization of the SiGe-channel profile. When a graded SiGe channel is used, hole mobilities as high as 220 cm/sup 2//V.s at 300 K and 980 cm/sup 2//V.s at 82 K are obtained. >

Si/SiGe epitaxial-base transistors. II. Process integration and analog applications

For pt. I, see ibid., vol. 3, p. 455-68 (1995). This part focuses on process integration concerns, first described in general terms and then detailed through an extensive review of both simple non-self-aligned device structures and more complex self-aligned device structures. The extension of SiGe device technology to high levels of integration is then discussed through a detailed review of a full SiGe HBT BiCMOS process. Finally, analog circuit design is discussed and concluded, with a description of a 12-bit Digital-to-Analog Converter presented to highlight the current status of SiGe technology. >

Understanding hot‐electron transport in silicon devices: Is there a shortcut?

Results of a Monte Carlo study of carrier multiplication in silicon bipolar and field‐effect transistors and of electron injection into silicon dioxide are presented. Qualitative and, in most cases, quantitative agreement is obtained only by accounting for the correct band structure, all relevant scattering processes (phonons, Coulomb, impact ionization), and the highly nonlocal properties of electron transport in small silicon devices. In addition, it is shown that quantization effects in inversion layers cause a shift of the threshold energy for impact ionization which is very significant for the calculation of the substrate current in field‐effect transistors. Conservation of parallel momentum, image‐force corrections, dynamic screening of the interparticle Coulomb interaction, and improvements to the WKB approximation are necessary to treat correctly the injection of electrons from silicon into silicon dioxide. The validity of models—analytic or Monte Carlo—which treat hot‐electron transport with oversimplified physical approximations is argued against. In a few words, there is no shortcut.

High-mobility modulation-doped SiGe-channel p-MOSFETs

A novel subsurface SiGe-channel p-MOSFET is demonstrated in which modulation doping is used to control the threshold voltage without degrading the channel mobility. A novel device design consisting of a graded SiGe channel, an n/sup +/ polysilicon gate, and p/sup +/ modulation doping is used. A boron-doped layer is located underneath the graded and undoped SiGe channel to minimize process sensitivity and maximize transconductance. Low-field hole mobilities of 220 cm/sup 2//V-s at 300 K and 980 cm/sup 2//V-s at 82 K were achieved in functional submicrometer p-MOSFETs.<<ETX>>

On the profile design and optimization of epitaxial Si- and SiGe-base bipolar technology for 77 K applications. I. Transistor DC design considerations

The DC design considerations associated with optimizing epitaxial Si- and SiGe-base bipolar transistors for the 77-K environment are examined in detail. Transistors and circuits were fabricated using four different vertical profiles, three with a graded-bandgap SiGe base, and one with a Si base for comparison. All four epitaxial-base profiles yield transistors with DC properties suitable for high-speed logic applications in the 77-K environment. The differences between the low-temperature DC characteristics of Si and SiGe transistors are highlighted both theoretically and experimentally. A performance tradeoff associated with the use of an intrinsic spacer layer to reduce parasitic leakage at low temperatures and the consequent base resistance degradation due to enhanced carrier freeze-out is identified. Evidence that a collector-base heterojunction barrier effect severely degrades the current drive and transconductance of SiGe-base transistors operating at low temperatures is provided. >

CMOS active pixel image sensors fabricated using a 1.8-V, 0.25-/spl mu/m CMOS technology

This paper reports the experimental results of the first CMOS active pixel image sensors fabricated using a high-performance 1.8 V, 0.25 /spl mu/m CMOS logic technology. No process modifications were made to the CMOS logic technology so that the impact of device scaling on the image sensing performance can be studied. This paper highlights the device and process design considerations required to enable CMOS as an image sensor technology.

Optimization of SiGe HBT technology for high speed analog and mixed-signal applications

SiGe HBTs have achieved record peak f/sub T/ values values and impressive digital circuit ECL RO delays but no analog circuit results have been reported. In this work we investigate the leverage of SiGe HBTs for analog circuits by optimizing the Ge-profile for a high /spl beta/V/sub A/ product and high f/sub T/ under the constraint of breakdown voltage and effective strain of the SiGe layer. Analytical calculations of /spl beta/, V/sub A/, and f/sub T/ of SiGe-HBTs as a function of Ge profile predict the largest performance advantage over Si BJTs for the most steeply graded Ge profile. SiGe-HBT transistors are fabricated with /spl beta/V/sub A/ products of 6160 V, BV/sub CEO/ of 3.5 V and f/sub max/ of 46 GHz, and compared to Si-BJTs fabricated with the same process. Digital performance is benchmarked by an ECL ring oscillator delay of 17.2 psec. The leverage for analog technology is demonstrated by fabrication of a 1 GHz SiGe-HBT 12 bit Digital to Analog Convertor.<<ETX>>