E.G. Villani

Monolithic Active Pixel Sensors (MAPS) in a quadruple well technology for nearly 100% fill factor and full CMOS pixels

In this paper we present a novel, quadruple well process developed in a modern 0.18 μm CMOS technology called INMAPS. On top of the standard process, we have added a deep P implant that can be used to form a deep P-well and provide screening of N-wells from the P-doped epitaxial layer. This prevents the collection of radiation-induced charge by unrelated N-wells, typically ones where PMOS transistors are integrated. The design of a sensor specifically tailored to a particle physics experiment is presented, where each 50 μm pixel has over 150 PMOS and NMOS transistors. The sensor has been fabricated in the INMAPS process and first experimental evidence of the effectiveness of this process on charge collection is presented, showing a significant improvement in efficiency.

A novel CMOS monolithic active pixel sensor with analog signal processing and 100% fill factor

We have designed and fabricated a CMOS monolithic active pixel sensor (MAPS) in a novel 0.18 micrometer image-sensor technology (INMAPS) which has a 100% fill factor for charged particle detection and full CMOS electronics in the pixel. The first test sensor using this technology was received from manufacture in July 2007. The key component of the INMAPS process is the implementation of a deep p-well beneath the active circuits. A conventional MAPS design for charged-particle imaging will experience charge sharing between the collection diodes and any PMOS active devices in the pixel which can dramatically reduce the efficiency of the pixel. By implementing a deep p-well, the charge deposited in the epitaxial layer is reflected and conserved for collection at only the exposed collection diode nodes. We have implemented two pixel architectures for charged particle detection. The target application for these pixels is for the sensitive layers of an electromagnetic calorimeter (ECAL) in an international linear collider (ILC) detector. Both pixel architectures contain four n- well diodes for charge-collection; analog front-end circuits for signal pulse shaping; comparator for threshold discrimination; digital logic for threshold trim adjustment and pixel masking. Pixels are served by shared row-logic which stores the location and time-stamp of pixel hits in local SRAM, at the bunch crossing rate of the ILC beam. The sparse hit data are read out from the columns of logic after the bunch train. Here we present design details and preliminary results.

A double-sided, shield-less stave prototype for the ATLAS Upgrade strip tracker for the High Luminosity LHC

A detailed description of the integration structures for the barrel region of the silicon strips tracker of the ATLAS Phase-II upgrade for the upgrade of the Large Hadron Collider, the so-called High Luminosity LHC (HL-LHC), is presented. This paper focuses on one of the latest demonstrator prototypes recently assembled, with numerous unique features. It consists of a shortened, shield-less, and double sided stave, with two candidate power distributions implemented. Thermal and electrical performances of the prototype are presented, as well as a description of the assembly procedures and tools.

Design and performance of a CMOS study sensor for a binary readout electromagnetic calorimeter

We present a study of a CMOS test sensor which has been designed, fabricated and characterised to investigate the parameters required for a binary readout electromagnetic calorimeter. The sensors were fabricated with several enhancements in addition to standard CMOS processing. Detailed simulations and experimental results of the performance of the sensor are presented. The sensor and pixels are shown to behave in accordance with expectations and the processing enhancements are found to be essential to achieve the performance required.

A double-sided silicon micro-strip Super-Module for the ATLAS Inner Detector upgrade in the High-Luminosity LHC

The ATLAS experiment is a general purpose detector aiming to fully exploit the discovery potential of the Large Hadron Collider (LHC) at CERN. It is foreseen that after several years of successful data-taking, the LHC physics programme will be extended in the so-called High-Luminosity LHC, where the instantaneous luminosity will be increased up to 5 × 1034 cm−2 s−1. For ATLAS, an upgrade scenario will imply the complete replacement of its internal tracker, as the existing detector will not provide the required performance due to the cumulated radiation damage and the increase in the detector occupancy. The current baseline layout for the new ATLAS tracker is an all-silicon-based detector, with pixel sensors in the inner layers and silicon micro-strip detectors at intermediate and outer radii. The super-module is an integration concept proposed for the strip region of the future ATLAS tracker, where double-sided stereo silicon micro-strip modules are assembled into a low-mass local support structure. An electrical super-module prototype for eight double-sided strip modules has been constructed. The aim is to exercise the multi-module readout chain and to investigate the noise performance of such a system. In this paper, the main components of the current super-module prototype are described and its electrical performance is presented in detail.

High voltage multiplexing for the ATLAS Tracker Upgrade

The increased luminosity of the HL-LHC will require more channels in the upgraded ATLAS Tracker, as a result of the finer detector segmentation, stemming from the otherwise too high occupancy. Among the many technological challenges facing the ATLAS Tracker Upgrade there is more an efficient power distribution and HV biasing of the sensors. The solution adopted in the current ATLAS detector uses one HV conductor for each sensor, which makes it easy to disable malfunctioning sensors without affecting the others, but space constraints and material budget considerations renders this approach impractical for the Upgraded detector. A number of approaches, including the use of the same HV line to bias several sensors and suitable HV switches, along with their control circuitry, are currently being investigated for this purpose. The proposed solutions along with latest test results and measurements will be described.

TPAC: A 0.18 micron MAPS for digital electromagnetic calorimetry at the ILC

For the ILC physics program, the detectors will need an unprecedented jet energy resolution. For the electromagnetic calorimeter, the use of a highly granular silicon-tungsten calorimeter has been proposed. We have developed a Monolithic Active Pixel-based readout for such a calorimeter, which will have extremely fine granularity and will make use of a digital readout. The first generation chip (TPAC1) implements a 168x168 array comprising 50x50 μm2 pixels. Each pixel has an integrated charge pre-amplifier and comparator. TPACI has been manufactured in the 0.18 μm INMAPS process which includes a deep p-well. We present results of the performance of the TPACI chip together with comparison to simulations and give an outlook to the second generation chip.

On exploiting a latchup-based detector via commercial CMOS technologies

The stimulated ignition of latchup effects caused by external radiation has so far proven to be a hidden hazard. Here this effect is described as a novel approach to detect particles by means of a solid-state device susceptible to latchup effects. In addition, the device can also be used as a circuit for reading sensors devices, leaving the capability of sensing to external sensors. The paper first describes the state-of-the-art of the project and its development over the latest years, then the present and future studies are proposed. An elementary cell composed of two transistors connected in a thyristor structure is shown. The study begins using traditional bipolar transistors since the latchup effect is originated as a parasitic circuit composed of such devices. Then, an equivalent circuit built up of MOS transistors is exploited, resulting an even more promising and challenging configuration than that obtained via bipolar transistors. As the MOS transistors are widely used at present in microelectronics devices and sensors, a latchup-based cell is proposed as a novel structure for future applications in particle detection, amplification of signal sensors and radiation monitoring.