E. L. Hu

Reactive‐ion etching of GaAs and InP using CCl2F2/Ar/O2

We describe the reactive ion etching of GaAs, InP, and their derivative compounds using an etch gas composed of CCl2F2, O2, and argon. Etching was generally carried out at pressures between 1 and 10 μ, and power densities below 0.8 W/cm2. Clean etch profiles were obtained with etch rates as high as 0.25 μm/min. A strong dependence of etch rate on pressure was observed with a maximum at 5 μ total pressure. The etch profiles exhibited a ’’negative undercut’’ character which was also dependent upon the total pressure.

50−nm silicon structures fabricated with trilevel electron beam resist and reactive‐ion etching

A trilevel electron beam resist has been used to make 25‐nm metal features on thick silicon substrates. Using this metal as a mask for reactive ion etching, silicon structures 0.33 μm deep have been fabricated. The resist consists of a thin upper layer of polymethylmethacrylate (PMMA), a middle layer of Ge, and a lower layer of co‐polymer of methylmethacrylate and methacrylic acid, P(MMA/MAA). High‐resolution patterns are written in the upper resist layer and are transferred to the lower layers by reactive‐ion etching. Completed resist stencils have 300‐nm high walls with near‐vertical profiles and are suitable for liftoff processing.

Reactive ion etching of LiNbO3

We describe the reactive ion etching of LiNbO3 in gas mixtures containing CCl2F2, CF4, O2, and Ar. The effects of gas composition and pressure, in the range 1–10‐μm total pressure are discussed. Because it is possible to replicate fine features (∼2000 A) with control of etch profiles, we expect the process to be used for three‐dimensional patterning of LiNbO3 for electro‐optic and acoustic‐optic devices.

Multilevel resist for lithography below 100 nm

Features as small as 25 nm have been made with electron-beam lithography using multilevel resists on thick silicon substrates. Liftoff patterning of metal lines and reactive ion etching of silicon have demonstrated the possibility of making device structures with lateral dimensions below 100 nm.

400‐Å linewidth e‐beam lithography on thick silicon substrates

Resist features as small as 200 A and gold lines as narrow as 400 A separated by 800‐A center to center have been fabricated on thick silicon. substrates. A two‐layer electron‐sensitive resist structure is employed consisting of an upper layer of polymethyl‐methacrylate and a lower layer of a copolymer of methacrylic acid and methyl methacrylate. Use of the more electron‐sensitive lower layer results in an undercut which provides clean lift‐off of the evaporated gold. Degradation in the pattern resolution by electrons backscattered from the substrate is minimized by the presence of the lower resist layer. This method provides the finest resolution lift‐off patterns reported.

Small‐area high‐current‐density Josephson junctions

Josephson junctions with areas of ∼10−9 cm2 and current densities of 105 A/cm2 are described. The junctions were patterned using a combination of optical lithography and oblique evaporation techniques. The junction width is limited by the lithographic resolution to about 1 μm. The junction length is determined essentially by the base‐electrode film thickness and can be as small as 1000 A. The moderate (∼10 Ω) normal resistances of these junctions combined with their short intrinsic RC times gives them potential for application in nonlatching Josephson logic and in quasiparticle mm‐wave mixers.

Ultrasmall superconducting tunnel junctions

Extremely small-area superconducting Josephson junctions have been fabricated using a newly developed electron-beam lithography technique. The junctions are composed of Pb-In base electrodes and Pb counter electrodes. Areas of the junctions range from 1 to 3 × 10^-10cm². The estimated capacitance is ∼10^-15F. Junctions have been produced with resistances of ∼100 Ω which have ∼20-percent hysteresis in the critical current at a temperature of 4 K.

Nonmetallic localization and interaction in one-dimensional (0.1 μm) Si MOSFETs

Abstract We have fabricated Si MOSFETs having parallel arrays of narrow (0.1 μm) conducting channels. We observe a divergent, nonmetallic decrease of conductance below 30 K that is in excellent quantitative agreement with the one-dimensional version of the combined theories for weak localization and interaction effects. We also observe structure in the conductance as a function of gate voltage that we attribute to random variations of the density of states, rather than the regular variations expected for simple one-dimensional quantization.

Vertical silicon membrane arrays patterned with tri-level e-beam resist

A high resolution, tri-level e-beam resist process has been developed which has produced, by liftoff, planar metal features as fine as 25 nm wide by 5 Μm long on thick Si substrates. The metal features have been used as masks for transfer of the pattern into the substrate itself, producing arrays of Si membranes, 50 nm wide, 0.3 pm high and extending 5 Μm in length. We compare the resolution of the tri-level system with that obtained for a previously reported bi-level system of similar composition.

Self‐aligned thin film structures with 1000 Å resolution

A two‐level e‐beam resist process is described which is capable of producing features under 1000 A in size. The process is compatible with oblique evaporation technique so that high‐accuracy alignment can be obtained in multiple‐layer device structures. Tunnel junction structures with areas as small as 10−10 cm2 have been fabricated. The estimated capacitance for such junctions is <10−15 F. Such structures have application in low‐capacitance Josephson logic circuits. The process is also applicable to fabrication of submicron MOM diodes and other devices which can be made using a lift‐off technique.