A.M. Voshchenkov

Non-overlapping super self-aligned BiCMOS with 87 ps low power ECL

It is demonstrated that high-speed bipolar and CMOS processes can be merged without compromise on either device. A NOVA (nonoverlapping super self-aligned) structure with an advanced epi/isolation process that reduces parasitic capacitances and resistances is reported. The scheme combines lateral autodoping free epi deposition with a novel fully recessed oxide process. This approach significantly simplifies the isolation process and is an important factor in achieving high speed with a conservative 1.5- mu m design rule. A high-speed frequency divider, a multiplexer, and a demultiplexer operating up to 4.1 GHz, 5.5 Gb/s, and 6.2 Gb/s, respectively, have been fabricated. The results show that NOVA BiCMOS is suitable for Gb/s digital VLSI application.<<ETX>>

89-GHz f/sub T/ room-temperature silicon MOSFETs

The authors report the implementation of deep-submicrometer Si MOSFETs that at room temperature have a unity-current-gain cutoff frequency (f/sub T/) of 89 GHz, for a drain-to-source bias of 1.5 V, a gate-to-source bias of 1 V, a gate oxide thickness of 40 AA, and a channel length of 0.15 mu m. The fabrication procedure is mostly conventional, except for the e-beam defined gates. The speed performance is achieved through an intrinsic transit time of only 1.8 ps across the active device region.<<ETX>>

A technique for rapidly alternating boron and arsenic doping in ion‐implanted silicon molecular beam epitaxy

This letter reports the use of boron ion implantation doping during simultaneous growth of silicon molecular beam epitaxy. It describes further a technique for epitaxial growth of abrupt silicon p‐n junctions by rapid changeover during growth between boron and arsenic ion beams. This is expected to be of importance in a variety of applications, including, for example, high speed bipolar junction transistors.

A 750MS/s NMOS latched comparator

THIS PAPER WILL DESCRIBE THE DESIGN of analog circuits integrated in a polysilicon gate NMOS technology with lp effective channel length devices’. In particular, a latched comparator with 4b input resolution at 750MS/s and a wideband amplifier with l0dB of voltage gain over a bandwidth of 1.25GHz, when driving 130fF of on-chip capacitance, will be reported. The comparator was designed primarily for application to high-speed flash A/D conversion, but is is also suitable for use in integrated broadband fiber optic receivers. Its circuit configuration differs from previous in that negative feedback is used in the preamplifier section to trade gain for bandwidth.

Nonoverlapping super self-aligned device structure for high-performance VLSI

The nonoverlapping super self-aligned structure (NOVA) is reported. Because of its nonoverlapping nature, this structure can be applied equally well to bipolar, CMOS, or BiCMOS processes. This structure effectively minimizes parasitic capacitance and resistance for both the MOS and bipolar devices. CMOS and bipolar devices are integrated into a high-performance BiCMOS technology. CMOS and emitter-coupled logic (ECL) ring oscillators with 1.5- mu m lithography are reported to have delays of 128 and 87 ps/stage, respectively.<<ETX>>

SiGMOS&#8212;A silicon gigabit/s NMOS technology

A n o v e l f i n e l i n e s i l i c o n NMOS technology, SiGMOS, has been deve loped to ach ieve as h i g h a s p o s s i b l e c i r c u i t s p e e d s . I n v e r t e r p r o p a g a t i o n d e l a y s p e r s t a t e of 78, 64 , 43 and 33 psec have been ob ta ined fo r dev ices wi th an e f f ec t ive wid th o f 5 .5 um and e f f e c t i v e c h a n n e l l e n g t h s o f 1 .25, 1 .00 , 0.75 and 0 . 5 um, r e s p e c t i v e l y . T h e s e a r e t h e s m a l l e s t d e l a y s p e r e f f e c t i v e c h a n n e l l e n g t h e v e r r e p o r t e d f o r a s i l i c o n MOS t echno logy , and t hey r ep resen t a f a c t o r o f two improvement compared t o mos t p rev ious r e su l t s .

Buried channel MOSFET's with gate lengths from 2.5 &#181;m to 700 &#197;

High resolution electron beam lithography has been used to fabricate ion implanted buried channel MOSFETs with gate lengths ranging from 0.4 µm to 700 Å. Similar devices were also fabricated on the same chip using optical lithography with gate lengths of 2.5 µm. These devices include some with the smallest lithographically defined gates ever made in silicon; similar devices should help define the limits to miniaturization in semiconducting devices.

In-situ low energy BF 2 + ion doping for silicon molecular beam epitaxy

An experimental study of the p-type ion dopant BF<inf>2</inf>+ in silicon molecular beam epitaxy (MBE) is described. BF<inf>2</inf>+ was used to dope MBE layers during growth to levels ranging from 1 × 10¹⁶/cm³to 4 × 10¹⁸/cm³over a growth temperature range of 650°C to 1000°C. The layers were evaluated using spreading resistance, chemical etching, and secondary ion mass spectroscopy. Complete dopant activation was observed for all growth temperatures. Remnant fluorine in the epitaxial layer was less than 2 × 10¹⁶/cm³in all cases. Diffused p-n junction diodes fabricated in BF<inf>2</inf>+-doped epitaxial material showed hard reverse breakdown characteristics.

Suppression of lateral autodoping from arsenic buried layer by selective epitaxy capping

An effective way to suppress lateral autodoping from the heavily arsenic-doped buried layer during silicon epitaxy is described. By using this simple technique, collector-substrate capacitance (C/sub cs/) is minimized. This process is ideal for high-speed BiCMOS and bipolar technology. A thin epilayer is first grown selectively on the buried layer. This selectively grown film suppresses the release of arsenic during the subsequent epi growth. High-performance bipolar devices have been fabricated in this epi material. Electrical measurements indicate that the crystalline quality is excellent.<<ETX>>

Lateral Autodoping Suppression by Selective Epitaxy Capping and Its Application in High Speed BiCMOS

fabrication. Other advanced technique like trench isolation may be considered. Trench isolation is, however, involved and expensive. A simple solution is to apply the recently reported selective epi growth (SEG)4-6). Fig.2 illustrates the process sequence. Single crystal silicon is selectively grown inside oxide windows. The highly doped buried layer is now capped. In addition, the oxide protects the off-buried layer region from the arsenic contamination. Subsequently, the oxide mask is removed and an epitaxy layer of desired doping is deposited. Lateral autodoping can be reduced by 2-3 orders of magnitude while maintaining a low arsenic buried layer sheet