E Liu

The influence of voids in solder joints on thermal performance and reliability investigated with transient thermal analysis

The thermal management of modern high power LEDs is essential for their life time. An important aspect is the thermal path from the heat generated in the LED die and phosphor, over the printed circuit board (PCB) to the heat sink. The temperature of the LED die depends on the quality of the solder joint between the LED package and the copper pads on the PCB. To evaluate the quality of the solder joint the transient thermal analysis is a powerful tool. In this paper the relative thermal resistance method is applied to detect the initial increase of the thermal resistance by voids in the solder joint and furthermore the impact of the initial voids on the reliability of the ceramic LED packages. The investigation in this paper reveals that the samples with voids have initially solely a slightly higher thermal resistance but the voids cause a significant faster thermal degradation during temperature shock test due to increased crack growth in the solder joint.

Analysis of new direct on PCB board attached high power flip-chip LEDs

Recent progress in wafer level packaging technologies has enabled high power Flip Chip (FC-LEDs), Chip Scale Package (CSP-LEDs) and Wafer Level LED Packages (WLP-LEDs) for direct assembly on printed circuit boards (PCB) for lighting application. The LEDs can be soldered with a SMT compatible reflow process on PCB. Packaging simplicity and flexibility, increased position accuracy, low thermal resistance and reduced cost has been the main motivation for these developments. In addition, the small chip sized LED package can enable on board level closer placement of the light emitting surfaces without the disturbing wire bond. This is a benefit, e.g. for optical design of LED matrix applications, in which multiple high power light pixels are switched individually and sharp contrast is required, as for automotive front lighting for instance. One major concern and bottleneck for high power FCLED attachment directly on PCB had been the mismatch between the coefficient of thermal expansion of the semiconductor material (GaN, InGaN) of the chip and the PCB. Adequate overall mechanical design of the FC-LED had to be developed. Also the electrical redistribution layer on the FC-LED is crucial for performance and reliability of FCLEDs. The reduction of one package level, i.e. the submount which functions also as heat spreader impacts the thermal performance. In the paper we evaluate potential of architectures based on the new WLP-LEDs and benchmark them with standard chip on board concepts and modules based on ceramic and lead frame packages. The requirements for the printed circuit boards (PCB) are investigated regarding electrical routing and thermal performance. Prototypes are assembled and the thermo-mechanical reliability of the FC-LED is investigated by temperature cycle tests.

The influence of the phosphor layer as heat source and up-stream thermal masses on the thermal characterization by transient thermal analysis of modern wafer level high power LEDs

Abstract In the last years Waver Level LED Packages (WLP-LEDs) were developed. They are thin film flip chips where the sapphire substrate remains attached on top of the epitaxial light emitting layer (EPI) which can be assembled directly on a printed circuit board. The thermal resistance and the thermal path of WLP-LED packages are measured by transient thermal analysis and transient finite element simulation. This study investigates the impact of the upstream thermal masses, i.e. the sapphire (SP), phosphor layer (PL) and the side coating (SC) on the transient thermal impedance curve and the cumulative structure function. It is shown that the standard approach to extract thermal properties by features (steps) within the structure function is misleading for thermal networks with upstream thermal load and distributed heat source (EPI and PL) because they influence the shape of the structure function. By transient thermal measurements and finite element (FE) simulation the transient thermal measurements are analysed to extract information about the thermal parameters and the thermal path. Starting from the analysis of the blue flip chip LED (FC-LED, no PL and no SC) the FE-model is set up. Stepwise the FE model is extended and the influence of the PL and the SC on the transient thermal measurement is investigated. A FE model is validated and calibrated which allows simulating the transient thermal curves of these modern LEDs. Using the model the impact of structural changes in the LED package on the transient thermal curves can be identified for reliability analysis.

Location resolved transient thermal analysis to investigate crack growth in solder joints

An innovative new test method, location resolved transient thermal analysis (LrTTA), is developed based on transient thermal measurement (TTM). LrTTA uses several distinct diodes on a test chip to detect the thermal performance of interfaces and assemblies. The temperature is measured by the forward voltage time dependent at different locations and inhomogeneities in the interface, e.g. cracks, voids and thickness variations, can be resolved. This investigation is necessary for analysis of the failures in solder joints since the local temperature can be strongly vary due to local bad thermal contact. For first experimental application of the method, a silicon thermal test chip with four different located temperature diodes was employed and soldered on an Aluminium Insulated Metal Substrate (Al-IMS) and exposed to temperature cycles. Transient thermal measurements were performed directly after assembly and after specific temperature shock cycle numbers (−40°C/+125°C). After data processing the increase of the thermal impedance of each diode between the initial “0” cycles and “n” cycles was obtained and correlated with crack distribution in the solder joint by X-ray and scanning acoustic microscopy images. In addition, a finite element (FE) model was set up and used to analyze the solder joint with and without voids and also the crack propagation in the solder joint during temperature shock testing.

New Method to Separate Failure Modes by Transient Thermal Analysis of High Power LEDs

A high reliability of light emitting diode (LED) light sources is essential for general and automotive lighting applications, where exchange of LED components is expensive. Thermal management of modern high power LEDs is crucial for their lifetime. An important aspect is the thermal path for heat conduction. Many different defects can have an influence on this path of an electronic system: on the one hand process failures during production, e.g. voids inside the solder joint, on the other hand typical failures induced by thermo-mechanical stress during their lifetime, like cracks in the solder joint or delamination in the package. The transient thermal analysis (TTA) is a powerful tool to detect changes in the thermal path. Due to improvements in the TTA method during the last years, not only cracks can be detected but also failure modes can be separated, and the root cause can be analyzed by support of transient finite element analysis. In this paper, transient thermal testing is applied and further developed, to monitor the structural integrity of new wafer level LED packages during thermal stress testing. Failure modes are defined and separated. For failure analysis the different defects are simulated by transient finite element analysis and correlated to the TTA results. The simulation results, that solder cracks increase the peak height of the derivative of the transient thermal curves (b(z)). A delamination of an inner layer of the LED package creates additionally to the increase of the peak height also a separation of the b(z) curves between 1 µs and 5 µs. Therefore a transient thermal measurement equipment with a dead time

The influence of phosphor layer and sidecoating on the thermal performance and the structure function of modern waver level high power LEDs

Many modern Waver Level LED Packages (WLP-LEDs) are thin film flip chips with the sapphire substrate attached on top of the epitaxial light emitting layer (EPI). This study targets to investigate the impact of the upstream thermal masses of the sapphire, the phosphor layer (PL) and the side coating (SC) on the transient thermal impedance curve and the cumulative structure function. It is shown that the standard approach to extract thermal properties by features (steps) within the structure function is not appropriate for this kind of LEDs. By transient Finite Element (FE) simulation the transient thermal measurements are analysed to extract information about the thermal parameters and the thermal path. Starting from the analysis of the blue flip chip LED (FC-LED) the FE-model is set up. Stepwise the FE model is extended and the influence of the PL and the SC on the transient thermal measurement is investigated.