E. Tutuc

Scaling of Al2O3 dielectric for graphene field-effect transistors

We investigate the scaling of Al2O3 dielectric on graphene by atomic layer deposition (ALD) using ultra-thin, oxidized Ti and Al films as nucleation layers. We show that the nucleation layer significantly impacts the dielectric constant (k) and morphology of the ALD Al2O3, yielding k = 5.5 and k = 12.7 for Al and Ti nucleation layers, respectively. Transmission electron microscopy shows that Al2O3 grown using the Ti interface is partially crystalline, while Al2O3 grown on Al is amorphous. Using a spatially uniform 0.6 nm-thick Ti nucleation layer, we demonstrate graphene field-effect transistors with top dielectric stacks as thin as 2.6 nm.

Chemical and physical interface studies of the atomic-layer-deposited Al2O3 on GaAs substrates

In this work, we study the chemical and physical properties of the interface between Al2O3 and GaAs for different surface treatments of GaAs. The interfacial layer between the high-κ layer and GaAs substrate was studied using x-ray photoelectron spectroscopy (XPS) and transmission electron microscopy (TEM). The reduction in native oxide layer was observed upon atomic layer deposition of Al2O3 on nontreated GaAs using trimethyl aluminum precursor. It was also observed that the sulfide treatment effectively mitigates the formation of the interfacial layer as compared to the surface hydroxylation using NH4OH. The electrical characteristics of GaAs capacitors further substantiate the XPS and TEM results.

Self-aligned inversion-type enhancement-mode GaAs metal-oxide-semiconductor field-effect transistor with Al2O3 gate dielectric

In this letter, we report fabrication of self-aligned inversion-type enhancement-mode GaAs metal-oxide-semiconductor (MOS) field-effect transistors with atomic layer deposition of Al2O3 gate dielectric directly on GaAs substrates using a simple ex situ wet clean of GaAs. Thermal stability of the gate stack was examined by monitoring the frequency dispersion behavior of GaAs MOS capacitors under different annealing conditions. A maximum drive current of ∼4.5μA∕μm was obtained for a gate length of 20μm at a gate overdrive of 2.5V. The threshold voltage and subthreshold slope were determined to be ∼0.4V and ∼145mV∕dec from the corresponding Id-Vg characteristics.

Realization of dual-gated Ge–SixGe1−x core-shell nanowire field effect transistors with highly doped source and drain

We demonstrate dual-gated germanium (Ge)-silicon germanium (SixGe1−x) core-shell nanowire (NW) field effect transistors (FETs) with highly doped source (S) and drain (D). A high-κ HfO2 gate oxide was deposited on the NW by atomic layer deposition, followed by TaN gate metal deposition. The S and D regions of NW were then doped using low energy (3 keV) boron (B) ion implantation with a dose of 1015 cm−2. The electrical characteristics of these devices exhibit up to two orders of magnitude higher current and an improved ON/OFF current ratio by comparison to dual-gated NW FET with undoped S/D.

Doping of Ge–SixGe1−x core-shell nanowires using low energy ion implantation

We investigate the doping of germanium (Ge)–silicon germanium (SixGe1−x) core-shell nanowires (NWs) by low energy (3 keV) boron (B) ion implantation. Ge–SixGe1−x core-shell NWs were implanted with B atoms at different doses from 1×1014 to 1×1015 cm−2, and subsequently annealed for dopant activation. Using four-point, gate-dependent resistance measurements, we determine the resistivity, doping levels, and contacts resistance of the B-doped Ge–SixGe1−x NWs. Our findings show that depending on the implantation dose, the doping level of B-doped NWs ranges from 1×1018 to 2×1020 cm−3.

Hall mobility measurements in enhancement-mode GaAs field-effect transistors with Al2O3 gate dielectric

We report the direct measurement of the inversion charge density and electron mobility in enhancement-mode n-channel GaAs transistors using gated Hall bars. The Hall data reveal the existence of a reduced mobile charge density in the channel due to significant charge trapping. The peak electron mobility was found to be relatively high (∼2140 cm2/V s), in agreement with inherent high carrier mobility of electrons in III-V materials.

Interfacial-oxygen-vacancy mediated doping of MoS 2 by high-κ dielectrics

Dielectric engineering using high-κ oxides, such as atomic layer deposited (ALD) Al₂O_x and HfO_x, has been in widespread use to enhance the mobility of molybdenum disulfide (MoS₂) based field effect transistors (FETs) [1,2]. This performance enhancement of MoS₂ FETs in a high-κ environment is mainly attributed to the screening of Coulomb scattering from charged impurities, as well as the quenching of homopolar phonon modes of MoS₂ [3]. However, the exact mechanism is still unclear. In this work, we demonstrate, using both experiment and theory, the n-doping of MoS₂ mediated by interfacial-oxygen-vacancies at the high-κ-MoS₂ interface, and propose a mechanism for the mobility enhancement effect in MoS₂ devices upon high-κ encapsulation.

Accurate inversion charge and mobility measurements in enhancement-mode GaAs field-effect transistors with high-k gate dielectrics

Recently, extensive studies have been conducted [1–5] in order to realize enhancement-mode III–V MOSFETs by improving the interface between gate oxide and III–V channel. The carrier mobility in advanced substrates is generally regarded as a figure of merit in benchmarking high-mobility channel materials against bulk Si substrates. However, charge trapping can be a source of error in mobility calculation using split C-V method for Si MOSFETs with high-k dielectrics [6]. On the other hand, magnetotransport measurements are suitable for direct measurement of inversion charge density (Ninv) and mobility in MOS devices with high-k gate dielectrics, where significant charge trapping makes evaluation of inversion charge density using split C-V method inaccurate. In this work, we employ gated-Hall-bar (GHB) structures to directly measure the inversion charge and mobility in a GaAs MOSFET.

Insights into interlayer tunnel FET performance improvement: Lessons learned from graphene hexagonal boron nitride heterostructures

We have explored ITFETs with varying thickness of graphene conduction layers. We have found that due to the increase in the DOS for thicker graphene, the resonance peaks are enhanced. However, due to the increase in the number of sub-bands and smaller spacing between the sub-bands for multi-layer graphene, especially Bernalstacked odd number of layer graphene with Dirac cone bands, the resonance peaks are more closely spaced together and result in either subdued NDR characteristics or no NDR at all. Although an even number of layer graphene offers fewer resonance peaks, we found that for thin interlayer hBN, bandgap opening causes the peaks to broaden.

Gate tunable resonant tunneling in graphene-based heterostructures and device applications

Electron tunneling is receiving increased emphasis as the physical mechanism of operation in emerging devices that seek to mitigate power dissipation issues in aggressively scaled CMOS technology. A tunneling field-effect transistors (TFET) consisting of a gated p-i-n junction is arguably the best known example. In a separate class of tunneling devices, consisting of two semiconducting layers separated by a barrier, the inter-layer tunneling current-voltage characteristics possess gate-tunable negative differential resistance [1]-[3], which is subsequently used to implement Boolean logic functions [4]. We describe here the fabrication, characterization, and benchmarking of inter-layer TFETs (ITFETs) using double bilayer graphene heterostructures separated by hexagonal boron-nitride dielectric as example [Fig. 1(a)].