Earl S. Schlegel

MOS Integrated Circuit Reliability

This paper presents information on the reliability of MOS integrated circuits based on p-channel enhancement-mode transistors, and describes their failure modes and mechanisms. The principal failure mechanisms were ion migration at the surface and oxide shorting. The results of experimental studies of the effects of variations in construction, processing, and levels of stress are presented, and are compared with other available information on MOS integrated circuit reliability. The failure rate for commercially available complex MOS arrays is on the order of 0.001 to 0.01 per 1000 h of operating life at 125°C for arrays containing approximately 600 p-channel transistors. This corresponds to a failure rate on the order of 5 × 10?6 to 5 × 10?5 per equivalent gate per 1000 h. The effects of device complexity, operating temperature, and other factors are discussed. A reliability prediction equation for MOS integrated circuits is derived from available information. An overall activation energy for functional failure mechanisms of approximately 5 kcal/mole (?0.2 eV/molecule) is considered applicable to typical MOS integrated circuits. Thus, the failure rate of MOS devices operated at 50°C ambient temperature can be predicted to be on the order of 10?6 to 10?5 per equivalent gate per 1000 h.

Thyristors with overvoltage self-protection

Power thyristors which are immune to destructive triggering by overvoltage transients have been designed, fabricated, and tested. A 10- mil deep well was etched in the gate region prior to the final p-type diffusion. This modified the forward blocking junction so that it avalanched at 2800V. The avalanche current provided a gate signal which turned on the thyristor and avoided destructive edge firing. Measurements of the infrared recombination radiation verified that overvoltage turn-on occurred at the gate region. With overvoltage triggering,the thyristors withstood follow-on currents of 40A from snubber discharges. Standard thyristors with no self-protection were destroyed by 0.5A. The self-protected thyristors were light-triggered devices with VRRM= 2800V and IDRM= 900A. Incorporation of the overvoltage self-protection feature increases device reliability and eliminates the need for overrating of blocking voltages to allow for transients.

Gate assisted turn-off thyristor with cathode shunts and dynamic gate

A 1000V, 200A gate-assisted turn-off thyristor (GATT) is described that was developed for, and is being used in, circuitry for space applications requiring high efficiency and reliability as well as small size and weight. The design features include an interdigitated shunted cathode, a dynamic gate, a means for optimizing the carrier lifetime level, and a bypass diode. The bypass diode is necessary to permit the combination of both dynamic turn-on and gate-assisted turn-off in the same device. Two versions of this diode are described. The device physics of gate-assisted turn-off will be reviewed. Based on this, improvements in the design will be described. It is shown that a prime failure mode can be eliminated and that the gate-assist signal voltage can be substantially decreased by employing a shunted cathode emitter. The test data show excellent turn-on characteristics due to the dynamic gate and the long perimeter of the edge of the main cathode. Turn-off times as short as 3 µsec are obtained. The effect of the gate-assist current on the turn-off time is described. The combination of controlling the carrier lifetime with a precisely controlled and easily variable irradiation dose of high energy electrons with gate assist current provides for simple, precision tailoring of the device characteristics to the intended application.