Eckhard Hennig

UVM-based verification of smart-sensor systems

In this contribution, we present a UVM-based methodology for mixed-signal smart-sensor systems. Our approach permits the validation of system functionality before implementation and to verify implementations on various levels of abstraction. The model-based verification approach also helps to build a scalable and re-usable framework, in which assertions and constrained random-stimuli are used to monitor and verify mixed-signal system behavior automatically. Along with the designed UVM -testbench architecture, we describe a novel solution for estimating the power consumption of digital block using application-specific random activity patterns generated during testbench runs.

Embedded tutorial: Analog-/mixed-signal verification methods for AMS coverage analysis

Analog-/Mixed-Signal (AMS) design verification is one of the most challenging and time consuming tasks of todays complex system on chip (SoC) designs. In contrast to digital system design, AMS designers have to deal with a continuous state space of conservative quantities, highly nonlinear relationships, non-functional influences, etc. enlarging the number of possibly critical scenarios to infinity. In this special session we demonstrate the verification of functional properties using simulative and formal methods. We combine different approaches including automated abstraction and refinement of mixed-level models, state-space discretization as well as affine arithmetic. To reach sufficient verification coverage with reasonable time and effort, we use enhanced simulation schemes to avoid conventional simulation drawbacks.

An improved low-power CMOS thyristor-based micro-to-millisecond delay element

We present a novel low-power CMOS thyristor-based delay element for delay durations in the micro- to millisecond ranges. Starting from a basic CMOS thyristor delay circuit, we propose several modifications to reduce the energy/delay ratio by a factor of four: The threshold voltage of the internal CMOS thyristor is raised and a pull-up/down current source is used to increase the delay duration and reduce the influence of subthreshold leakage current on integration time and nonlinearity. A second CMOS thyristor stage increases the steepness of the transition slopes, thereby reducing shunt currents in subsequent stages during the switching event. The circuit was designed and fabricated in a commercial 0.35-μm CMOS process. Measurements were performed on a ring oscillator comprising three instances of the proposed delay element. By varying the bias currents of the elements, the delay duration can be tuned over more than three decades from 4 μs to 22 ms with excellent linearity.

A low-voltage low-power CMOS time-domain temperature sensor accurate to within [−0.1,+0.5] °C From −40 °C To 125 °C

We present a novel CMOS on-chip temperature sensor for use in low-voltage low-power applications. The sensor uses diode-connected BJTs to generate a PWM signal whose duty cycle is proportional to absolute temperature with high accuracy over a wide temperature range. The duty cycle is determined with a simple digital counter and converted to a digital code. Compared to other time-domain temperature sensors, our design requires only a single bias current and one comparator to generate the PWM signal. After a digital calibration at two temperature points, the sensor is accurate to within [-0.1, +0.5] °C in the temperature range from - 40 °C to 125°C and ±0.1 °C from 0°C to 125°C. The sensor has been fabricated in a 0.35-μm CMOS technology. It draws only 2.5 μA from a 1.4-V supply, corresponding to a power dissipation of 3.5 μW.

Temporal decoupling with error-bounded predictive quantum control

Virtual prototyping of integrated mixed-signal smart-sensor systems requires high-performance co-simulation of analog frontend circuitry with complex digital controller hardware and embedded real-time software. We use SystemC/TLM 2.0 in combination with a cycle-count accurate temporal decoupling approach to simulate digital components and firmware code execution at high speed while preserving clock cycle accuracy and, thus, real-time behavior at time quantum boundaries. Optimal time quanta ensuring real-time capability can be calculated and set automatically during simulation if the simulation engine has access to exact timing information about upcoming communication events. These methods fail in case of non-deterministic, asynchronous events resulting in a possibly invalid simulation result. In this paper, we propose an extension of this method to the case of asynchronous events generated by blackbox sources from which a-priori event timing information is not available, such as coupled analog simulators or hardware in the loop. Additional event processing latency and/or rollback effort caused by temporal decoupling is minimized by calculating optimal time quanta dynamically in a SystemC model using a linear prediction scheme. For an example smart-sensor system model, we show that quasi-periodic events that trigger activities in temporally decoupled processes are handled accurately after the predictor has settled.

Frequency compensation of closed-loop feedback amplifier systems

In this paper we consider application-specific frequency compensation of integrated circuit feedback amplifiers through computer-aided analysis and design of closed-loop systems. We employ our symbolic circuit analysis program Analog Insydes to derive transfer functions or poles and zeros of uncompensated amplifiers in closed-loop configuration in analytic form. Then, it will be shown how systematic examination of the resulting symbolic expressions can help to find and evaluate alternative circuit parameter modifications by way of which frequency compensation can be achieved.

An ultra-low power capacitance extrema and ratio detector for electrostatic energy harvesters

We present a novel ultra-low power capacitance extrema and modulation ratio detector for electrostatic micro vibration energy harvesters. The circuit signals the points in time where a varying harvester capacitance Cn(t) reaches its minimum and maximum values o min and o max in each oscillation period. A novel feature is that the circuit allows the capacitance modulation ratio ac = Cmax/Cmin between two consecutive extrema to be determined digitally. Using a self-clocked charge pumping scheme implemented with two low-power comparators and a pulse generator, our detector circuit keeps the voltage across a dedicated sense capacitor within a predefined margin around a fixed reference level. Transitions through capacitance extrema are indicated by polarity reversals of the charge packets. The number of charge packets transferred between two polarity reversals is nonlinearly but uniquely related to ac. The proposed circuit was implemented and fabricated in a commercial 0.35-/xm CMOS process. Measurements were performed using a rotating capacitor with Cmax = 150 pF and adjustable ac spinning with up to 110 Hz. Transitions through capacitance extrema were measured for ac = 1.3 ... 4.4 and were signalled accurately within the systematic time resolution limits of the method. In the presented configuration, the circuit draws a current of 60 nA from a 3.8-V supply.

A four-channel GNSS front-end IC for a compact interference- and jamming-robust multi-antenna Galileo/GPS receiver

We present a four-channel GNSS front-end IC for a compact interference- and jammer-robust multi-antenna sub-sampling receiver for Galileo El-B/C and GPS LI signals. The front end includes four coherent RF-to-IF signal paths with an intermediate frequency of 75.42 MHz, a common PLL frequency synthesizer, which generates the 1500-MHz local-oscillator signal, and an I2C interface for parameter adjustment. The front end exhibits a gain of 83 dB, a noise figure of 2.8 dB, and an input-referred 1-dB compression point of -73.5 dBm preventing the front end from saturation while jammed. A path-to-path isolation of at least 30 dB leads to a high spatial resolution. The power consumption is 231.7 mW and 255.7 mW with and without interferers, respectively.

A new method for automated generation of compensation networks — The EDA Designer Finger

In this paper a new frequency compensation method based on automatic topology modification of analog amplifier circuits is presented. Starting from an uncompensated circuit topology in closed-loop configuration, a capacitance is inserted between each pair of nodes. Subsequently, the set of inserted capacitances is reduced to a manageable size using a selection algorithm based on eigenvalue sensitivity calculation. Finally, the remaining capacitances are sized by a numerical optimization method. The presented method is demonstrated on a tran-simpedance amplifier design for an industrial HDTV application.