Eric Schäfer

Compact antenna array receiver for robust satellite navigation systems

A compact navigation receiver comprising a decoupled and matched four-element L1-band antenna array with an inter-element separation of a quarter of the free-space wavelength is presented in this paper. We investigate the impact of the decoupling and matching network on the robustness of the navigation receiver. It is observed that in order to achieve high robustness with a compact antenna array, it is necessary to employ a decoupling and matching network, particularly in case of three spatially separated interferers. Furthermore, we study the influence of the polarization impurity of the compact planar antenna array on the equivalent carrier-to-interference-plus-noise ratio (CINR) of the receiver when impinged with different numbers of diametrically polarized interference signals. It is shown that the higher-order modes possess strong polarization impurity, which may halve the available degrees-of-freedom for nulling in the presence of linear-polarized interferers, using a conventional null-steering algorithm. We verify the robustness of the designed compact receiver by means of a complete global-navigation-satellite-system demonstrator. It is shown that the maximum jammer power that is allowed us to maintain the CINR above 38 dBHz with three interferers can be improved by more than 10 dB if a decoupling and matching network is employed.

Noise characterization of a multi-channel receiver using a small antenna array with full diversity for robust satellite navigation

The employment of a DMN in small antenna arrays results in an increased antenna noise temperature due to increased ohmic losses. On the other hand, it minimizes the amplifier noise contribution considerably, thus reducing the equivalent system noise temperature. Therefore, the use of a DMN for small antenna arrays displaying full diversity is not only beneficial but necessary for optimizing receiver performance. The analysis sketched here will be extended to null-steering or interferer-cancellation scenarios.

Beamforming in compact antenna arrays for robust satellite navigation

In this paper the robustness of a four-element compact navigation antenna array against continuous-wave interferers is investigated. The compact antenna array is integrated with an analog decoupling and matching network to mitigate the mutual coupling between the antenna elements and restore efficient diversity gain. It is observed that the network improves the equivalent carrier-to-interference-plus-noise ratio by at least 3 dB in most directions for a three-interferer scenario. For a single, there is little benefit of the decoupling and matching network. However, the function of the array is intimately related to the performance of the front-end. Due to the unequal saturation of the first-stage low-noise receivers, the network provides the opportunity to select at least one channel remaining operational in the linear regime. This feature yields additional robustness to such compact receivers for detection and tracking in the presence of one strong interferer.

An improved low-power CMOS thyristor-based micro-to-millisecond delay element

We present a novel low-power CMOS thyristor-based delay element for delay durations in the micro- to millisecond ranges. Starting from a basic CMOS thyristor delay circuit, we propose several modifications to reduce the energy/delay ratio by a factor of four: The threshold voltage of the internal CMOS thyristor is raised and a pull-up/down current source is used to increase the delay duration and reduce the influence of subthreshold leakage current on integration time and nonlinearity. A second CMOS thyristor stage increases the steepness of the transition slopes, thereby reducing shunt currents in subsequent stages during the switching event. The circuit was designed and fabricated in a commercial 0.35-μm CMOS process. Measurements were performed on a ring oscillator comprising three instances of the proposed delay element. By varying the bias currents of the elements, the delay duration can be tuned over more than three decades from 4 μs to 22 ms with excellent linearity.

A contribution towards model-based design of application-specific MEMS

Abstract The design process of heterogeneous systems containing electro-mechanical components and electronic circuits involves expert knowledge, methods, and tools from different engineering domains. Cost-efficient research and development of such heterogeneous systems requires a systematic design flow without gaps. A contribution towards this global goal is presented in this article. A development and synthesis tool for one-dimensional accelerometer MEMS has been implemented, calculating sensor solutions and generating the models and layouts required for a hierarchical design flow in an automatic, module-based approach. Utilizing this flow, different accelerometers have been designed, manufactured, and characterized. A dedicated readout ASIC was developed to validate their dynamic behaviour.

An ultra-low power capacitance extrema and ratio detector for electrostatic energy harvesters

We present a novel ultra-low power capacitance extrema and modulation ratio detector for electrostatic micro vibration energy harvesters. The circuit signals the points in time where a varying harvester capacitance Cn(t) reaches its minimum and maximum values o min and o max in each oscillation period. A novel feature is that the circuit allows the capacitance modulation ratio ac = Cmax/Cmin between two consecutive extrema to be determined digitally. Using a self-clocked charge pumping scheme implemented with two low-power comparators and a pulse generator, our detector circuit keeps the voltage across a dedicated sense capacitor within a predefined margin around a fixed reference level. Transitions through capacitance extrema are indicated by polarity reversals of the charge packets. The number of charge packets transferred between two polarity reversals is nonlinearly but uniquely related to ac. The proposed circuit was implemented and fabricated in a commercial 0.35-/xm CMOS process. Measurements were performed using a rotating capacitor with Cmax = 150 pF and adjustable ac spinning with up to 110 Hz. Transitions through capacitance extrema were measured for ac = 1.3 ... 4.4 and were signalled accurately within the systematic time resolution limits of the method. In the presented configuration, the circuit draws a current of 60 nA from a 3.8-V supply.

A four-channel GNSS front-end IC for a compact interference- and jamming-robust multi-antenna Galileo/GPS receiver

We present a four-channel GNSS front-end IC for a compact interference- and jammer-robust multi-antenna sub-sampling receiver for Galileo El-B/C and GPS LI signals. The front end includes four coherent RF-to-IF signal paths with an intermediate frequency of 75.42 MHz, a common PLL frequency synthesizer, which generates the 1500-MHz local-oscillator signal, and an I2C interface for parameter adjustment. The front end exhibits a gain of 83 dB, a noise figure of 2.8 dB, and an input-referred 1-dB compression point of -73.5 dBm preventing the front end from saturation while jammed. A path-to-path isolation of at least 30 dB leads to a high spatial resolution. The power consumption is 231.7 mW and 255.7 mW with and without interferers, respectively.