Edil S. Tavares Fernandes

Conditional execution: an approach for eliminating the basic block barriers

Abstract In this paper we present the CONDEX machine model: a VLIW architecture supporting the conditional execution concept. The model consists of multiple and independent functional units that can operate in paralle. By interpreting the parallel code derived from a suite of test programs, we evaluated the performance of some CONDEX machine configurations. In addition to the description of this new architecture model, the paper presents the main aspects of the project.

Effects of Building Blocks on the Performance of Super-Scalar Architectures

The inherent low level parallelism of Super-Scalar architectures plays an important role in the processing power provided by these machines: independent functional units promote opportunities for executing several machine operations simultaneously. From the viewpoint of the hardware designer it is very important to assess the influence of each functional unit, and the way they communicate, on the overall performance of the machine. Particularly, it is highly desirable to determine an upper bound in the number of additional functional units which give significant performance improvement ratios. This work describes experiments that have been carried out to assess the effect of alternative instruction issue mechanisms, multiple functional units, instruction queues, common data bus and other hardware solutions on the performance of Super-Scalar machines. The assessment was obtained by interpreting non optimized object code fo an actual processor on some basic machine models. The paper outline the main aspects of the research, and shows that speed-up ratios of up to 3.35 times were observed during the interpretation of benchmark programs.

MPH - a hybrid parallel machine

Abstract This paper describes the design and realization of MPH, a Hybrid Parallel Machine, which is intended to be used as a tool for research in parallel computing. MPH is a multiprocessor system whose processors are arranged according to a hypercubic topology but with interprocessor communication being realized through memory segments which are shared by each pair of processors. The resulting machine incorporates the characteristics of both loosely and tightly coupled architectures, hence its hybrid nature. In addition to the design and implementation issues, the paper also describes the research potential of MPH, and the current stage of the work.

Microarchitecture modelling through ADL

ADL is an Architecture Description Language that has been developed to model computer architectures at different levels of detail, as for instance, at the microarchitecture level. Target architectures described in ADL are processed by the support system of the language which generates an interpreter program related to the description of the target machine. The interpreter reproduces the behavior of the architecture being modeled, including the interpretation of the target code. In addition to a brief review of the language and the implementation details of its support system, this paper also shows some methods to deal with target machine parallelism, and the modeling of two microprogrammable machines.

The Effect of the Speculation Depth on the Performance of Superscalar Architectures

Speculative execution is a key concept to increase the performance of superscalar processors. Given accurate branch prediction mechanisms, the efficiency of speculative execution is mainly determined by the speculation depth. In this work, we evaluate the pressure of speculative execution on the resource requirements of a typical superscalar architecture.

Functionality Distribution on a Superscalar Architecture

This paper deals with the distribution of functionality among the functional units of a superscalar processor. Starting with configurations including identical functional units capable of executing any instruction, we have assessed the effect provoked by replacing these complex units with specialized units to execute memory access and branch instructions. Our experiments show that the maximum speedup ratios obtained by configurations equipped with eight complex units can also be achieved by machines with the same number of simpler units.

Load balancing in superscalar architectures

New techniques are increasing the degree of instruction-level parallelism exploited by processors. Recent superscalar implementations include multiple functional units, allowing the parallel execution of several instructions from the same application program. The trend towards an expansion of the number of hardware resources is likely to continue in future superscalar designs, and in order to maximize the processor throughput, the computational load must be balanced among these resources by the dynamic instruction-issuing algorithm. We investigate the effect on performance caused by the way instructions are distributed among the functional units of superscalar processors. Our results show that a performance gain of up to 38% can be obtained when the instructions are evenly distributed among the functional units.

Evaluating the cost of conditional branches on the performance of superscalar machines

Abstract This paper presents a study of the impact of conditional branch instructions on the performance of Superscalar processors. By interpreting non-optimised code of a real processor on various configurations derived from a Superscalar architecture model, we have evaluated the execution time percentages in which the associative dispatch algorithm remains idle, waiting for the completion of conditional branch instructions. In addition, we have assessed the volume of instruction level parallelism that can be extracted from application programs if the target machine is equipped with an omniscient branch predictor.

Dispatching simultaneous instructions

Abstract Conventional processor can be characterized by the sequential nature in which machine instructions are dispatched: only one instruction is issued each time, and the next one will be started after the conclusion of the current one. However, the machine performance can be significantly improved if the hardware is able to issue several instructions to be executed simultaneously. In this work we describe some experiments that have been carried out to assess the effect of alternative instruction dispatching algorithms on the overall performance of machines comprising several independent functional units. The paper presents the main aspects of the project, and shows that reduction ratios up to 78% in the processing time required by some benchmark programs can be obtained by issuing multiple instructions.

An environment for concurrent programming in Pascal

Abstract This paper presents the specification and implementation of a kernel supporting an environment oriented towards the development and execution of concurrent programs written in an extension of PASCAL. The environment is based on the TURBO PASCAL which was extended with constructs providing mechanisms to express and synchronize the concurrent execution of processes. In addition to the specification and implementation details of the kernel, the paper also outlines the use of the environment in the development of parallel programs, and describes the current stage of the work which should lead to the migration of the environment to a parallel host machine.