Eliseu M. Chaves Filho

Design and Implementation of the MorphoSys Reconfigurable ComputingProcessor

In this paper, we describe the implementation of MorphoSys, a reconfigurable processing system targeted at data-parallel and computation-intensive applications. The MorphoSys architecture consists of a reconfigurable component (an array of reconfigurable cells) combined with a RISC control processor and a high bandwidth memory interface. We briefly discuss the system-level model, array architecture, and control processor. Next, we present the detailed design implementation and the various aspects of physical layout of different sub-blocks of MorphoSys. The physical layout was constrained for 100 MHz operation, with low power consumption, and was implemented using 0.35 μm, four metal layer CMOS (3.3 Volts) technology. We provide simulation results for the MorphoSys architecture (based on VHDL model) for some typical data-parallel applications (video compression and automatic target recognition). The results indicate that the MorphoSys system can achieve significantly better performance for most of these applications in comparison with other systems and processors.

The MorphoSys Parallel Reconfigurable System

This paper introduces MorphoSys, a parallel system-on-chip which combines a RISC processor with an array of coarse-grain reconfigurable cells. MorphoSys integrates the flexibility of general-purpose systems and high performance levels typical of application-specific systems. Simulation results presented here show significant performance enhancements for different classes of applications, as compared to conventional architectures.

MorphoSys: case study of a reconfigurable computing system targeting multimedia applications

In this paper, we present a case study for the design, programming and usage of a reconfigurable system-on-chip, MorphoSys, which is targeted at computation-intensive applications. This 2-million transistor design combines a reconfigurable array of cells with a RISC processor core and a high bandwidth memory interface. The system architecture, software tools including a scheduler for reconfigurable systems, and performance analysis (with impressive speedups) for target applications are described.

The MorphoSys dynamically reconfigurable system-on-chip

MorphoSys is a system-on-chip which combines a RISC processor with an array of reconfigurable cells. The important features of MorphoSys are coarse-grain granularity dynamic reconfigurability and considerable depth of programmability. The first implementation of the MorphoSys architecture, the M1 chip, is currently at an advanced stage and it will operate at 100 MHz. Simulation results indicate significant performance improvements for different classes of applications, as compared to general-purpose processors. Meanwhile, MorphoSys can provide the potential hardware platforn for the evolvable hardware (EH) simulation with the help of the software.

MorphoSys: a reconfigurable architecture for multimedia applications

We describe the MorphoSys reconfigurable system, which combines a reconfigurable array of processor cells with a RISC processor core and a high bandwidth memory interface unit. We introduce the array architecture, its configuration memory, inter-connection network, role of the control processor and related components. Architecture implementation is described in brief and the efficacy of MorphoSys is demonstrated through simulation of video compression (MPEG-2) and target-recognition applications. Comparison with other implementations illustrates that MorphoSys achieves higher performance by up to 10X.

The Dynamic Trace Memorization Reuse Technique

Dynamic Trace Memoization (DTM) is a reuse technique that employs memoization tables to skip the execution of sequences of redundant instructions. For the SPECInt95 benchmark programs, DTM delivers performance improvements from 5% to 21% with an average of 9.3%. Moreover, DTM attains twice the average speedup of two other previously proposed reuse mechanisms for a subset of the SPECInt95 benchmarks.

HiPCrypto: a high-performance VLSI cryptographic chip

Data security is an important issue in todays computer networks. This paper presents the HiPCrypto chip, which implements the IDEA cryptographic algorithm. HiPCrypto is oriented towards computer network applications demanding high throughput. Its architecture exploits both the spatial and the temporal parallelism available in the IDEA algorithm. When operating at a 53 MHz clock, HiPCrypto can encrypt/decrypt at data rates up to 3.4 Gbps.

MorphoSys: A Reconfigurable Processor Trageted to High Performance Image Application

This paper addresses the design idea of the MorphoSys Reconfigurable processor developed by the researchers in the UC, Irvine. With the demand to perform the multimedia operations efficiently, it is one of the directions that general processor needs to incorporate with some reconfigurable computing units, like FPGA. In MorphoSys project, we successfully propose a prototype to fulfill the above trend, which is comprised of a simplified general purpose MIPS-like RISC processor, called TinyRISC and 8×8 coarse grained reconfigurable cells, organized as SIMD architecture. MorphoSys is realized using 0.35um technology, and runs at 100Mhz with impressive performance enhancement compared with other architectures.

The Effect of the Speculation Depth on the Performance of Superscalar Architectures

Speculative execution is a key concept to increase the performance of superscalar processors. Given accurate branch prediction mechanisms, the efficiency of speculative execution is mainly determined by the speculation depth. In this work, we evaluate the pressure of speculative execution on the resource requirements of a typical superscalar architecture.

Functionality Distribution on a Superscalar Architecture

This paper deals with the distribution of functionality among the functional units of a superscalar processor. Starting with configurations including identical functional units capable of executing any instruction, we have assessed the effect provoked by replacing these complex units with specialized units to execute memory access and branch instructions. Our experiments show that the maximum speedup ratios obtained by configurations equipped with eight complex units can also be achieved by machines with the same number of simpler units.