Edmund J. Winder

B2H6 PLAD Doped PMOS Device Performance

Plasma doping (PLAD) achieves high wafer throughput by directly extracting ions across the plasma sheath. PLAD profiles are typically surface peaked instead of retrograde as obtained from beamline (BL) implant. It may require optimization of PLAD energy and dose in order to match BL doping results. From device optimization point of view, it is necessary to understand the impact of doping parameters to device characteristics. In this paper we present the PMOS device performance with the poly gate and source drain (SD) implants carried out using B2H6 PLAD. The BL control conditions are 2–5 keV 11B+ 4–6×1015 cm−2. Equivalent device performance for p+ poly gate doping is obtained using PLAD with B2H6 / H2. In SD doping using same gas mixture, nearly 50% reduction in SD contact resistance is observed in the PLAD splits. The reduction in SD contact resistance leads to 10–15% increase in device on‐current, hence demonstrating the process advantages of using PLAD in addition to having a high wafer throughput.

Process Control in Production‐Worthy Plasma Doping Technology

As the semiconductor industry continues to scale devices of smaller dimensions and improved performance, many ion implantation processes require lower energy and higher doses. Achieving these high doses (in some cases ∼1×1016 ions/cm2) at low energies (<3 keV) while maintaining throughput is increasingly challenging for traditional beamline implant tools because of space‐charge effects that limit achievable beam density at low energies. Plasma doping is recognized as a technology which can overcome this problem. In this paper, we highlight the technology available to achieve process control for all implant parameters associated with modem semiconductor manufacturing.

Plasma doping: production worthy solution for 65nm and beyond technology nodes

65nm and beyond advanced logic and DRAM devices will require decreasing junction depths and poly thickness at increasing doses. Present beam-line technology will suffer decreasing throughput during this transition as a result of space charge effects. Plasma doping is a well characterized alternative to beam-line technology that meets the doping requirements for <65nm ITRS technology nodes. This is accomplished at superior throughput levels which are largely energy insensitive. The simplicity of the plasma doping tool design and maturing process control features offer a promising future for production worthiness of this technique. Varians PLAD tool has demonstrated advanced logic USJ SDE/SD formation as well as advanced DRAM poly and SD doping capability. In this paper we present as-implanted and annealed SIMS profiles to highlight the sub-kV doping capability of the PLAD system for PMOS transistor fabrication and its impact on the R/sub s/ vs. X/sub J/ figure of merit. TEM data will also be presented to show lack of residual damage after a high nominal dose implant which agrees well with low junction leakage observed on PLAD doped devices. The production worthiness of the processes mentioned above is demonstrated with uniformity, repeatability, metals purity and particle performance comparable to that attainable with beam-line implants.