Edwin A. Arevalo

Ultra-shallow Carborane molecular implant for 22-nm node p-MOSFET performance boost

In this paper, for the first time, Carborane molecular implant is shown to provide performance boost applicable for both 22nm Low Power and High Performance applications. The impact of ultra-shallow Carborane incorporation into pMOS S/D-extension was investigated. It was found that the activation of surface Boron was enhanced by the ultra-shallow carbon incorporation inherent to the Carborane molecule. PMOS Transistor characteristics demonstrate that drive current, short channel effect, overlap capacitance as well as leakage are significantly improved by the chemical and physical effects of the Carborane molecule.

Approaches to USJ Formation Beyond Molecular Implantation

As junction depth requirements approach sub 10 nm and the sensitivity to residual implant damage continues to increase, the capability to produce abrupt, shallow profiles while maintaining low residual damage becomes a difficult challenge. Implantation induced amorphization has been widely applied to reduce channeling tails of implanted dopant profiles for integrated circuit manufacturing. This has been required to meet aggressive junction depth targets. The problem, however, is that pre‐amorphization creates high defect densities that remain near the former amorphous‐crystalline interface post anneal. These end of range (EOR) defects become of greater concern as the industry begins to move towards millisecond anneal technologies. Millisecond anneal, while capable of close to diffusionless activation and abrupt junctions, has caused concern for its inability to fully repair these EOR defects. There has been a recent focus on removing traditional PAI through molecular implantation with limited success. Tow...

B2H6 PLAD Doped PMOS Device Performance

Plasma doping (PLAD) achieves high wafer throughput by directly extracting ions across the plasma sheath. PLAD profiles are typically surface peaked instead of retrograde as obtained from beamline (BL) implant. It may require optimization of PLAD energy and dose in order to match BL doping results. From device optimization point of view, it is necessary to understand the impact of doping parameters to device characteristics. In this paper we present the PMOS device performance with the poly gate and source drain (SD) implants carried out using B2H6 PLAD. The BL control conditions are 2–5 keV 11B+ 4–6×1015 cm−2. Equivalent device performance for p+ poly gate doping is obtained using PLAD with B2H6 / H2. In SD doping using same gas mixture, nearly 50% reduction in SD contact resistance is observed in the PLAD splits. The reduction in SD contact resistance leads to 10–15% increase in device on‐current, hence demonstrating the process advantages of using PLAD in addition to having a high wafer throughput.

New Approaches to Ultra Shallow Junction Formation by Molecular Implantation and Millisecond Laser Spike Annealing

Scaling of source/drain extension junctions continues to be a major focus for sub 45 nm planar CMOS process development. Device scalability, drive current, and leakage performance are determined by junction depth, activation, and residual disorder. These requirements have driven ion implants into the deep sub-keV regime and integration of millisecond anneals for activation. In this paper, we introduce the formation of extension junctions using thermally stable boron containing molecular implant which alleviates productivity concerns with sub-keV implantation and runs on a standard high current implanter. In combination with advanced millisecond sub-melt laser anneal, p-n junctions with high activation and negligible dopant profile movement are produced. Limiting diffusion and maximizing activation with optimized dopant concentration, effect of different amorphization schemes, and the use of diffusion modifiers such as carbon will also be discussed in the context of millisecond laser anneals. In addition, the role of implantation in minimizing residual disorder after laser anneals and its relevance to junction leakage is discussed.

Advanced doping and millisecond annealing for ultra-shallow junctions for 65 nm and beyond

To meet the requirements of smaller devices while still maintaining high performance, it is necessary to form very shallow source/drain extensions with very high activation. Although significant progress has been made in meeting these requirements as outlined in the 2003 ITRS, continued progress in meeting the needs for the 65 nm technology generation and beyond remain a challenge. It will no longer be sufficient to consider the doping (ion implantation) and activation (annealing) steps independently. Both must be optimized together as a process sequence or module. This paper will survey the requirements for USJ doping and activation for the 65 nm node and beyond. Some recent results of the annealing of shallow P2LAD-doped silicon wafers using Vorteks fRTP millisecond flash lamp annealing will be presented and some discussion of the extendibility and applicability of these techniques will be presented

Process Control in Production‐Worthy Plasma Doping Technology

As the semiconductor industry continues to scale devices of smaller dimensions and improved performance, many ion implantation processes require lower energy and higher doses. Achieving these high doses (in some cases ∼1×1016 ions/cm2) at low energies (<3 keV) while maintaining throughput is increasingly challenging for traditional beamline implant tools because of space‐charge effects that limit achievable beam density at low energies. Plasma doping is recognized as a technology which can overcome this problem. In this paper, we highlight the technology available to achieve process control for all implant parameters associated with modem semiconductor manufacturing.

Plasma doping: production worthy solution for 65nm and beyond technology nodes

65nm and beyond advanced logic and DRAM devices will require decreasing junction depths and poly thickness at increasing doses. Present beam-line technology will suffer decreasing throughput during this transition as a result of space charge effects. Plasma doping is a well characterized alternative to beam-line technology that meets the doping requirements for <65nm ITRS technology nodes. This is accomplished at superior throughput levels which are largely energy insensitive. The simplicity of the plasma doping tool design and maturing process control features offer a promising future for production worthiness of this technique. Varians PLAD tool has demonstrated advanced logic USJ SDE/SD formation as well as advanced DRAM poly and SD doping capability. In this paper we present as-implanted and annealed SIMS profiles to highlight the sub-kV doping capability of the PLAD system for PMOS transistor fabrication and its impact on the R/sub s/ vs. X/sub J/ figure of merit. TEM data will also be presented to show lack of residual damage after a high nominal dose implant which agrees well with low junction leakage observed on PLAD doped devices. The production worthiness of the processes mentioned above is demonstrated with uniformity, repeatability, metals purity and particle performance comparable to that attainable with beam-line implants.