Edson Borin
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Publication
Featured researches published by Edson Borin.
international conference on supercomputing | 2009
Cheng Wang; Youfeng Wu; Edson Borin; Shiliang Hu; Wei Liu; Dave Sager; Tin-Fook Ngai; Jesse Fang
The performance of single-threaded programs and legacy binary code is of critical importance in many everyday applications. However, neither can hardware multi-core processors directly speed up single-threaded programs, nor can software automatic parallelizing compilers effectively parallelize legacy binary code and irregular applications. In this paper, we propose a framework and a set of algorithms to dynamically parallelize single-threaded binary programs. Our parallelization is based on program slicing and explores both instruction-level parallelism (ILP) and thread-level parallelism (TLP). To significantly reduce the critical path of the parallel slices, our slicing algorithms exploit speculation to cut rare dependences, and use well-designed program transformations to expose parallelism. Furthermore, because we transparently parallelize binary code at runtime, we perform slicing only on program hot regions. Our experiments demonstrate that the proposed speculative slicing approach extracts more parallelism than any known slicing based parallelization schemes. For the SPEC2000 benchmarks, we can achieve 3x parallelism with infinite number of threads, and 1.8x parallelism with 4 threads.
ieee international symposium on workload characterization | 2009
Edson Borin; Youfeng Wu
In recent years, dynamic binary translation has emerged as an important tool with many real world applications. Besides supporting legacy binary code and ISA virtualization, it enables innovative co-designed microarchitectures and allows transparent binary instrumentation. The dynamic nature of the translation usually incurs extra execution overhead and many research works had proposed software and hardware solutions to minimize the overhead [1, 2]. In this paper, we analyze our dynamic binary translator performance and depict the main sources of overhead in details. We classify the translation operations and associated overhead into five major categories, and quantify their contribution to the overall overhead. Based on the analysis and detailed evaluation, we identify and point out the most promising solutions to address the overhead problem. We believe this study is an important first step toward the grand goal of zero-overhead dynamic binary translation.
symposium on code generation and optimization | 2010
Edson Borin; Youfeng Wu; Cheng Wang; Wei Liu; Mauricio Breternitz; Shiliang Hu; Esfir Natanzon; Shai Rotem; Roni Rosner
Dynamic binary translation is a key component of Hardware/Software (HW/SW) co-design, which is an enabling technology for processor microarchitecture innovation. There are two well-known dynamic binary optimization techniques based on atomic execution support. Frame-based optimizations leverage processor pipeline support to enable atomic execution of hot traces. Region level optimizations employ transactional-memory-like atomicity support to aggressively optimize large regions of code. In this paper we propose a two-level atomic optimization scheme which not only overcomes the limitations of the two approaches, but also boosts the benefits of the two approaches effectively. Our experiment shows that the combined approach can achieve a total of 21.5% performance improvement over an aggressive out-of-order baseline machine and improve the performance over the frame-based approach by an additional 5.3%.
ACM Sigarch Computer Architecture News | 2005
Edson Borin; Cheng Wang; Youfeng Wu; Guido Araujo
Shrinking microprocessor feature size will increase the soft-error rates to unacceptable levels in the near future. While reliable systems typically employ hardware techniques to address soft-errors, software techniques can provide a less expensive and more flexible alternative. This paper presents a control-flow error classification and proposes new software based control-flow error detection techniques. The new techniques are better than the previous ones in the sense that they detect errors in all the branch-error categories. We also compare the performance of our new techniques with that of the previous ones using our dynamic binary translator.
international symposium on computer architecture | 2010
João Paulo Porto; Guido Araujo; Edson Borin; Youfeng Wu
Program performance can be dynamically improved by optimizing its frequent execution traces. Once traces are collected, they can be analyzed and optimized based on the dynamic information derived from the programs previous runs. The ability to record traces is thus central to any dynamic binary translation system. Recording traces, as well as loading them for use in different runs, requires code replication to represent the trace. This paper presents a novel technique which records execution traces by using an automaton called TEA (Trace Execution Automata). Contrary to other approaches, TEA stores traces implicitly, without the need to replicate execution code. TEA can also be used to simulate the trace execution in a separate environment, to store profile information about the generated traces, as well to instrument optimized versions of the traces. In our experiments, we showed that TEA decreases memory needs to represent the traces (nearly 80% savings).
Archive | 2010
Mauricio Breternitz; Youfeng Wu; Cheng Wang; Edson Borin; Shiliang Hu; Craig B. Zilles
Archive | 2005
Edson Borin; Cheng C. Wang; Youfeng Wu
Archive | 2010
Cheng Wang; Edson Borin; Youfeng Wu; Shiliang Hu; Wei Liu; Mauricio Breternitz
Archive | 2011
Youfeng Wu; Shiliang Hu; Edson Borin; Cheng C. Wang; Mauricio Breternitz; Wei Liu
Archive | 2011
Cheng Wang; Wei Liu; Edson Borin; Jr. Mauricio Breternitz; Youfeng Wu; Shiliang Hu