Eduard Bertran

On the Wiener and Hammerstein models for power amplifier predistortion

This paper presents a comparative study on the suitability of using Hammerstein or Wiener models to identify the power amplifier (PA) nonlinear behavior considering memory effects. This comparative takes into account the operational complexity regarding the identification process as well as their accuracy to follow the PA behavior. Both identified PA models will be used to estimate a Hammerstein based predistorter in order to see which model combination provides better linearization results. In addition, two adaptive algorithms for predistorting both PA models are compared in terms of accuracy and converge speed.

A New Digital Predictive Predistorter for Behavioral Power Amplifier Linearization

This letter presents a new digital adaptive predistorter (PD) for power amplifier (PA) linearization based on a nonlinear auto-regressive moving average (NARMA) structure. The distinctive characteristic of this PD is its straightforward deduction from the NARMA PA model, without the need of using an indirect learning approach to identify the PD function. The PD itself presents a NARMA structure, and hence it can be quickly implemented by means of lookup tables. Single and multicarrier modulated signals collected from a three-stage LDMOS class AB PA, with a maximum output power of 48-dBm CW have been used to validate the linearity performance of this new predictive predistorter

FPGA Implementation of a Real-Time NARMA-Based Digital Adaptive Predistorter

This paper presents the design of a nonlinear autoregressive moving average (NARMA) digital adaptive predistorter (DAPD) for power amplifier (PA) linearization consisting of a low-complex closed-loop architecture. Both the predistortion function and the adaptation algorithm are fully implemented in a field-programmable gate array (FPGA) device, without the need for using any additional coprocessor. The proposed predistortion architecture is capable to compensate for both the PA nonlinear distortion and memory effects. Moreover, this DAPD allows almost real-time adaptation without interrupting the normal transmission. The computational complexity introduced by this DAPD is studied in this paper. The proposed theoretical design is implemented in an FPGA, whereas the linearization performance of the DAPD is validated through simulated and experimental results.

Digital Predistortion of Envelope Tracking Amplifiers driven by slew-rate limited envelopes

This paper presents a new Digital Predistorter (DPD) to compensate for nonlinear distortion that arises in Envelope Tracking (ET) Power Amplifiers (PAs) driven by slew-rate limited versions of the real signals envelope. The slower version of the transmitted signals envelope is used to cope with the slew-rate and bandwidth limitations of Envelope Amplifiers (EAs). Unfortunately, the use of slower versions of the real signals envelope as the drain modulator generates a special kind of nonlinear memory effects. This paper shows experimental results that prove that is possible to compensate for these nonlinear memory effects that appear when exciting the supply of a RF linear PA with a slew-rate limited version of the envelope.

On the use of GPS receivers in railway environments

This paper presents the electromagnetic interference effects on the performance of locomotive onboard Global Positioning System (GPS) receivers due to the railway environment. The evaluation of the maximum tolerated interferences around a train is presented by taking into account European Committee for Electrotechnical Standardization and the International Electrotechnical Commission normative, Mobile Radio for Railway Networks in Europe, and experimental results. These interference levels are used to study the performance of a hardware GPS receiver operating at different modes and considering the possible levels of GPS signal L1 at the earth surface. From the obtained results, it is possible to conclude the reliability of a low-cost GPS receiver for train positioning even if the train equipment has been designed at the threshold of the current normative.

Order reduction of wideband digital predistorters using principal component analysis

This paper presents how to apply order reduction in wide-band digital predistortion (DPD) linearizers using the principal component analysis (PCA) technique. This method is tested in a wireless backhauling transmitter where four 28 MHz adjacent subcarrier transmission of M-QAM signals are considered. The DPD has to counteract not only the PA nonlinear behavior, but also its dynamics. This may results critical when considering wideband signals since the number of coefficients required to model memory effects can grow dramatically. By applying the PCA technique, the number of essential parameters can be significantly reduced. In addition, a strategy to minimize the computational cost of finding the optimal coefficients is also presented. A test-bed for evaluating the DPD linearization performance of the RF subsystem when PCA is applied was deployed and experimental results are presented in this paper.

On the performance of Cartesian feedback and feedforward linearization structures operating at 28 GHz

Some performance results of the Cartesian feedback and feedforward linearization techniques applied to a class-A power amplifier operating at 28 GHz are presented. The performance of the combination of HMMC-5040 (driver) and HMMC-5033 (power amplifier) is used as benchmark for simulation analysis. This analysis is addressed to show the key aspects on spectral regrowth due to phase margin and loop gain for Cartesian feedback, and time delay, phase and gain mismatch for feedforward. A 16 QAM digital signal at 10 Mbits/s filtered with a squared raised cosine filter with /spl alpha/=0, 25 is used as test signal.

A Methodology to Model and Predistort Short-Term Memory Nonlinearities in Power Amplifiers

This paper presents a study on the suitability of using certain dynamic nonlinear models for modelling the power amplifier (PA) with memory effects in terms of accuracy (that is how it resembles the real data) and complexity (number of coefficients needed in the parameterization). Later, focusing in the digital predistorter (PD) model identification and taking into account the main predistortion quality indicators (adjacent channel power ratio ACPR, error vector magnitude EVM at the transmitter, and the bit error rate BER at the receiver), a Hammerstein based predistorter is proposed and a new empirical method for choosing the best delays contributing in the Hammerstein model is presented. This previous empirical study permits the use of the most significant delays contributing in the predistortion process. Therefore the digital predistorter remains scalable which is an important factor of merit since it has to be capable of being implemented in a digital signal processor

A method for real-time generation of slew-rate limited envelopes in envelope tracking transmitters

This paper shows a method for generating slew-rate limited envelopes in order to accomplish the slew-rate restrictions of the envelope driver in envelope tracking transmitters. The proposed algorithm can run in real-time and it is implemented in a digital front-end of a Software Radio system. Simulation results and conclusions are provided to validate the methodology. Moreover, experimental results of an FPGA implementation are also provided.

Slew-rate limited envelopes for driving envelope tracking amplifiers

This paper presents a practical application of a method for generating slew-rate limited envelopes in order to drive the dynamic supply of envelope tracking (ET) power amplifiers (PAs). The proposed method results useful to generate slower versions of the transmitted signals envelope to cope with the slew-rate and bandwidth limitations of envelope amplifiers. Moreover, this paper shows experimental results comparing the performance of ET when exciting the drain of a PA (based in a GaN transistor) with both the envelope of the signal and the slew-rate limited version of the envelope.