Eduardas Bareiša

Research and development of teaching software engineering processes

The teaching system on software engineering in Kaunas University of Technology is investigated. This system lets students to experience the realistic software engineering problems and environments. In the development of an education system one has to take into account new challenges caused by Software Development Globalization. Organizing the software engineering process we implemented some key practices of repeatable level of Capability Maturity Model. Educational issues that showed up in performing Master study programmes are presented.

Functional delay test generation based on software prototype

The paper presents two methods of functional delay test development based on the software prototype as well as the results of their application to benchmark circuits. The first method is used to construct the functional delay test on the base of a pin pair test generated at the functional level for detection of stuck-at faults at the gate-level. The constructed test is a single input transition test. The latter appears to be quite large. Therefore, we provide the method for compacting it. The compacted single input transition test becomes a multi-input transition test. The second method is used to generate a multi-input transition test. The generated functional test pattern pairs possess function-robust and/or function-non-robust properties. The introduction of the function-non-robust property enriches the functional delay test. The presented test construction approach based on the software prototype allows obtaining a functional delay test, which detects the transition faults at the gate-level of a circuit quite completely.

Test generation at the algorithm-level for gate-level fault coverage

Abstract We present a test generation approach that enables to construct functional test patterns at early stages of the design according to the software prototype of the circuit. The presented approach is based on an input–output pin pair and an input–input–output pin triplet fault models. The basic properties of these models are analyzed. Random test generation was implemented on the base of these fault models. ISCAS’85 and ITC’99 benchmark circuits were used for the experiments. The obtained results for the presented fault models were compared with the gate level test generation. The problem of termination of random search is explored and the solution is proposed.

Software testing using imprecise OCL constraints as oracles

Many software testing techniques are targeted on test data generation. Only a few of them provide an automatic way to verify if software behaves correctly using generated test data. We propose to use software model as imprecise test oracle. UML modelling language extension OCL can be used as test oracle. Imprecise OCL constraints can be viewed as expressions which define expected results within some ranges of possible values. Imprecise OCL constraints can be viewed as expressions which define expected results within some ranges of possible values. When software is executed using generated test data the output is verified against imprecise OCL constraints. If output does not satisfy imprecise OCL constrains, unit under test definitely contains bugs. And if output satisfies imprecise OCL constraints the tester can assume that unit under test has no bugs.

Functional test generation remote tool

The same circuit may be described at algorithmic, behavioral or gate level. Test generation is usually performed for every level separately. We introduce a test generation approach based on test selection by means of simulation at algorithmic level of circuit description. The generated test could be applied to VHDL behavioral level as test bench. This test shows high fault coverage at equivalent gate level. The test selection procedure relies on the model of input stuck-at faults transmissions to output. The application of test frames allows sequential circuits to consider like combinational ones. The proposed method is implemented in the test generation program that is available on the Internet as freeware. The experiment shows efficiency of the proposed method.

Functional fault models for non-scan sequential circuits

Abstract The paper presents two functional fault models that are applied for functional delay test generation for non-scan synchronous sequential circuits: the pin pair state (PPS) fault model and the pin pair full state (PPFS) fault model. The PPS fault model deals with the pairs of stuck-at faults on the primary inputs and the primary outputs, as well as, with the pairs of stuck-at faults on the previous state bits and the primary outputs. The PPFS fault model encompasses the PPS model, and additionally deals with the pairs of stuck-at faults on the primary inputs and the next state bits, as well as, with the pairs of stuck-at faults on the previous state bits and the next state bits. The main factor in assessing the quality of obtained test sequences was the transition fault coverage at the gate level of the selected according to the appropriate fault model test sequences from the generated randomly ones. The experimental results demonstrate that the implementation using presented functional fault models allow selecting the test sequences from the initial test set without the loss of transition fault coverage in many cases, and the number of the selected test sequences is much lesser than that of the initial test set. This result demonstrates that the functional delay test can be generated using the presented functional delay fault models before structural synthesis of the circuit.

The Testing Method Based on Image Analysis for Automated Detection of UI Defects Intended for Mobile Applications

Large amounts of defects found in applications are classified as user interface defects. As more and more applications are provided for smart phones, it is reasonable to test those applications on various possible configurations of mobile devices such as screen resolution, OS version and custom layer. However, the set of mobile devices configurations is quite large. Developers are limited to testing their applications on all possible configurations.

Unit tests construction based on business rules

Software unit testing involves generating or creating test data and specifying a test oracle. The test oracle verifies if software under testing behave correctly when it is given test data as an input.

Text Semantics and Layout Defects Detection in Android Apps Using Dynamic Execution and Screenshot Analysis.

The paper presents classification of the text defects. It provides a list of user interface text defects and the method based on static/dynamic code analysis for detecting defects in Android applications. This paper proposes a list of static analysis rules for detecting every defect and the tool model implementing those rules. The method and the tool are based on the application of multiple Android application emulators, execution of the application through certain execution paths on multiple hardware and software configurations while taking application screen-shots. The defects are identified by running analysis rules on each taken screen-shot and searching for defect patterns. The results are presented by testing sample Android application.

The Study of Gender Equality in Information Sciences Research Institutions in Lithuania

The aim of this paper is to define the problem and to present the gender equality gaps existing in Information Sciences and Technology (IST) research institutions in Lithuania and to deeply analyze the problem in case study.