Vacius Jusas

EEG Dataset Reduction and Feature Extraction Using Discrete Cosine Transform

Brain-Computer interface (BCI) systems require intensive signal processing in order to form control signals for electronic devices. The majority of BCI systems work by reading and interpreting cortically evoked electro-potentials across the scalp via an electro-encephalogram (EEG). An important factor affecting the efficiency of BCI is the number of EEG features. To reduce the number of features is an important way to improve the speed. In this paper, we consider application of discrete cosine transform (DCT) on EEG signals. DCT takes correlated input data and concentrates its energy in just first few transform coefficients. This method is used as a feature extraction step and allows data size reduction without losing important information. For classification we are using artificial neural networks with different number of hidden neurons and training functions. We conclude that the method can be successfully used for the feature extraction and dataset reduction.

Functional delay test generation based on software prototype

The paper presents two methods of functional delay test development based on the software prototype as well as the results of their application to benchmark circuits. The first method is used to construct the functional delay test on the base of a pin pair test generated at the functional level for detection of stuck-at faults at the gate-level. The constructed test is a single input transition test. The latter appears to be quite large. Therefore, we provide the method for compacting it. The compacted single input transition test becomes a multi-input transition test. The second method is used to generate a multi-input transition test. The generated functional test pattern pairs possess function-robust and/or function-non-robust properties. The introduction of the function-non-robust property enriches the functional delay test. The presented test construction approach based on the software prototype allows obtaining a functional delay test, which detects the transition faults at the gate-level of a circuit quite completely.

Test generation at the algorithm-level for gate-level fault coverage

Abstract We present a test generation approach that enables to construct functional test patterns at early stages of the design according to the software prototype of the circuit. The presented approach is based on an input–output pin pair and an input–input–output pin triplet fault models. The basic properties of these models are analyzed. Random test generation was implemented on the base of these fault models. ISCAS’85 and ITC’99 benchmark circuits were used for the experiments. The obtained results for the presented fault models were compared with the gate level test generation. The problem of termination of random search is explored and the solution is proposed.

EEG Dataset Reduction and Classification Using Wave Atom Transform

Brain Computer Interface (BCI) systems perform intensive processing of the electroencephalogram (EEG) data in order to form control signals for external electronic devices or virtual objects. The main task of a BCI system is to correctly detect and classify mental states in the EEG data. The efficiency (accuracy and speed) of a BCI system depends upon the feature dimensionality of the EEG signal and the number of mental states required for control. Feature reduction can help improve system learning speed and, in some cases, classification accuracy. Here we consider Wave Atom Transform (WAT) of the EEG data as a feature reduction method. WAT takes input data and concentrates its energy in a few transform coefficients. WAT is used as a data preprocessing step for feature extraction. We use artificial neural networks (ANNs) for classification and perform research with varying number of neurons in a hidden layer and different network training functions (Levenberg-Marquardt, Conjugate Gradient Backpropagation, Bayesian Regularization). The novelty of the paper is the application of WAT in the EEG data processing. We conclude that the method can be successfully used for feature extraction and dataset feature reduction in the BCI domain.

FSM Based Functional Test Generation Framework for VHDL

The major challenge for the semiconductor industry is to design devices in short time with complex logical functionality. At the very top of the list of challenges to be solved is verification. The goal of the verification is to ensure that the design meets the logical functional requirements as defined in the logical functional specification. Verification of the devices takes 40 to 70 per cent of the total development effort for the design. The increasing complexity of hardware designs raises the need for the development of new techniques and methodologies that can provide the verification team with the means to achieve its goals quickly and with limited resources.

Functional test generation remote tool

The same circuit may be described at algorithmic, behavioral or gate level. Test generation is usually performed for every level separately. We introduce a test generation approach based on test selection by means of simulation at algorithmic level of circuit description. The generated test could be applied to VHDL behavioral level as test bench. This test shows high fault coverage at equivalent gate level. The test selection procedure relies on the model of input stuck-at faults transmissions to output. The application of test frames allows sequential circuits to consider like combinational ones. The proposed method is implemented in the test generation program that is available on the Internet as freeware. The experiment shows efficiency of the proposed method.

Combining Software and Hardware Test Generation Methods to Verify VHDL Models

Verification is an important part of the chip design process. Design is usually represented in hardware description language (HDL). Contemporary HDLs have constructs that are characteristic to software programs. Therefore, the methods to automatically generate test for software programs can be applied to generate test for HDL models. One of such methods is symbolic execution. We present a framework to generate test benches for HDL models. The framework combines the methods of symbolic execution and control flow graph, which are usually used in the context of software programs, with finite state machine that is characteristic for HDL models. The framework is implemented in Python programming language. We experimented with ITC’99 benchmark suite and compared the performance of our framework with similar research. Our obtained results outperformed the results taken from similar research. DOI: http://dx.doi.org/10.5755/j01.itc.42.4.4261

Functional fault models for non-scan sequential circuits

Abstract The paper presents two functional fault models that are applied for functional delay test generation for non-scan synchronous sequential circuits: the pin pair state (PPS) fault model and the pin pair full state (PPFS) fault model. The PPS fault model deals with the pairs of stuck-at faults on the primary inputs and the primary outputs, as well as, with the pairs of stuck-at faults on the previous state bits and the primary outputs. The PPFS fault model encompasses the PPS model, and additionally deals with the pairs of stuck-at faults on the primary inputs and the next state bits, as well as, with the pairs of stuck-at faults on the previous state bits and the next state bits. The main factor in assessing the quality of obtained test sequences was the transition fault coverage at the gate level of the selected according to the appropriate fault model test sequences from the generated randomly ones. The experimental results demonstrate that the implementation using presented functional fault models allow selecting the test sequences from the initial test set without the loss of transition fault coverage in many cases, and the number of the selected test sequences is much lesser than that of the initial test set. This result demonstrates that the functional delay test can be generated using the presented functional delay fault models before structural synthesis of the circuit.

A Methodology and Tool for Investigation of Artifacts Left by the BitTorrent Client

The BitTorrent client application is a popular utility for sharing large files over the Internet. Sometimes, this powerful utility is used to commit cybercrimes, like sharing of illegal material or illegal sharing of legal material. In order to help forensics investigators to fight against these cybercrimes, we carried out an investigation of the artifacts left by the BitTorrent client. We proposed a methodology to locate the artifacts that indicate the BitTorrent client activity performed. Additionally, we designed and implemented a tool that searches for the evidence left by the BitTorrent client application in a local computer running Windows. The tool looks for the four files holding the evidence. The files are as follows: *.torrent, dht.dat, resume.dat, and settings.dat. The tool decodes the files, extracts important information for the forensic investigator and converts it into XML format. The results are combined into a single result file.

Investigation of Artifacts Left by BitTorrent Client on the Local Computer Operating under Windows 8.1

BitTorrent client application is a popular tool to download large files from Internet, but this application is quite frequently used for illegal purposes that are one of the types of cybercrimes. If order to fight against this type of cybercrime we carried out the research, during which we investigated the evidences left by BitTorrent client application in registry under Windows 8.1 operating system. The experiment was carried out in three steps: installation, download, and uninstallation. The snapshots of registry were taken and compared prior and after each step. Changes in Windows registry were collected and joined into tables. The experiment revealed that BitTorrent client application creates Windows registry artefacts that can contain information which might be used as evidence during an investigation. The evidence remains in the registry even after the removal of the application, although it can really prove the fact of usage of the application only. The investigation of file system can reveal the purpose and the contents of the BitTorrent client session. DOI: http://dx.doi.org/10.5755/j01.itc.44.4.13082