Edward C. Stewart

Wafer-level Fault Detection and Classification on a photo track in a high volume fab

We will discuss Advanced Micro Devicess (AMD) Fault Detection and Classification (FDC) program strategy and our six-step project template that we have identified that must be addressed for any successful FDC effort. We will discuss the recent development and implementation of a wafer-level FDC system on a TEL CLEAN TRAC ACT 8 photo track system in AMDs Fab25, a high volume microprocessor factory. We will present our approach to designing and implementing this FDC system and demonstrate its ability to automatically identify specific wafers within a lot that require manual review. Upon manual review, the decision can be made to rework the specific wafers or the lot.