Edward David Moreno

Prefetching and Multithreading Performance in Bus-Based Multiprocessors with Petri Nets

The large latency of memory accesses is a major obstacle in obtaining high processor utilization in large scale shared-memory multiprocessors. Access to remote memory is likely to be slow, compared to the ever-increasing speeds of processors. Thus, any scalable architecture must rely on techniques that can cope with the large latency of memory accesses to reduce/hide/tolerate remote-memory-access latencies.

True causes of jagged effect in image display raster devices: reconstruction error

This paper analyzes the jagged effect that occurs in image display raster devices. Our main goal is to identify the true causes of the jagged effect, and the initial hypothesis is that between sampling and reconstruction errors the latter is the only cause. We conclude that reconstruction is the only cause of the jagged effect.

A Flexible and Parameterized Architecture for Multicore Microcontroller

This paper presents the concept and preliminary tests in FPGA of a specific architecture for a flexible multicore microcontroller. It is aimed to intermediate complexity embedded applications. A previous exact characterize of the microcontroller model and its target applications is a costly-time task, and it depends mostly on experience of the engineers and programmers. The proposed architecture can aid the development of new applications, for selecting resources during the development phase. We have designed a prototype in FPGA which is working and running applications with up seven CPUs.

A VLSI architecture for image reconstruction

In this paper we propose a VLSI architecture for an image reconstructor. The architecture implements in hardware the Two Dimensional Normalized Sampled Finite Sinc Reconstructor (NSFSR 2-D) reconstruction technique. Based on validation results, we conclude the proposed architecture implements correctly the NSFSR 2-D and is optimized in performance when compared with a software-based implementation.

Performance analysis of Linux containers for high performance computing applications

Although cloud infrastructures can be used as High Performance Computing (HPC) platforms, many issues from virtualisation overhead have kept them almost unrelated. However, with advent of container-based virtualisation, this scenario acquires new perspectives because this technique promises to decrease the virtualisation overhead, achieving a near-native performance. In this work, we analyse the performance of a container-based virtualisation solution - Linux Container (LXC) - against a hypervisor-based virtualisation solution - KVM - under HPC activities. For our experiments, we consider CPU and (network and inter-process) communication performance. Results show that hypervisor type can impact distinctly in performance according to resource used by HPC application.

A VLIW-based cryptoprocessor on FPGAs architecture and performance issues (abstract only)

This work shows a new architecture for a VLIW-based cryptoprocessor, which is implemented on FPGAs. The cryptoprocessor was designed to execute symmetric cryptography algorithms preferentially. To do so, special modules (such SBOX and PERBIT for substitution and permutation operations, respectively) were described in order to increase the performance and simplify the source program. The cryptoprocessor was described using VHDL language, and a prototype was synthesized and implemented in a FPGA Virtex generating occupation statistic data and temporary performance. It is important to note that the special modules which makes the cryptoprocessor different are not specific to a certain cryptography algorithm, and they were projected in order to be preconfigured according to the characteristics of the algorithm to be executed.

Cache Performance on Parallel Hash Join Algorithms

We investigate the effect that caches, particularly caches for remote accesses, have on the performance of hash join algorithms. The join is a computationally intensive operation of relational databases and it is used in many important applications. Thus, there are considerable studies on the parallel hash join. However, most of the previous researches do not show how cache is affecting the performance of these algorithms. In this paper, we show the impact and benefits of network caches on the overall performance of parallel hash join algorithms running on modern shared memory architecture.

Tuning Shared Network Cache Size vs. Second-Level Cache Size in Clusters-Based Multiprocessors

In this paper we evaluate the effectiveness of shared network caches in cluster-based multiprocessors when the L2-cache size is increased. Our simulation results are obtained with execution driven simulation and a 32 processors system. We stimulate the system with SPLASH-2 programs.

Efficiency of remote access caches in future SMP-based CC-NUMA multiprocessors: initial results

The paper evaluates the benefits of adding a shared remote access cache (RAC) in SMP based CC-NUMA multiprocessors. We consider symmetric multiprocessor (SMP) nodes as the building blocks for a multiprocessor due to its cost effectiveness, which makes SMP nodes an attractive choice for CC-NUMA designers. We base our experimental evaluation of the future architectures on realistic hardware parameters for state of the art systems components. What distinguishes our work from previous research is that we consider future processors and adequate values to access time to memory/caches/RACs, network and SMP bus speed. We simulate six applications from the SPLASH-2 benchmark suite to compare the performance application of our baseline architecture (current machines) and future architectures (approach-1: slow network and approach-2: fast network) when RACs are used in the system. The simulation results show that for a 32-processor system based on four-processor SMP nodes, the RACs improve the overall system performance by up to 32%, 28% and 20% for our baseline, approach-1, and approach-2, respectively. Similarly, the RACs diminish the execution time by up to 35%, 28.2% and 22% for two-processor SMP nodes. Therefore, our principal conclusion is that RACs reduce the execution time in future systems which have four or two 500 MHz processors per node.

A new image manipulation method in communication systems

This paper presents and analyzes a new method for image manipulation in communication systems. The main goals are to optimize the use of image manipulation resources and this optimization will be accomplished with a high image display quality. Based on results, we conclude that our main goals were achieved.