Fábio Dacêncio Pereira

A Hardware Architecture for Integrated-Security Services

There are numerous techniques, methods and tools to promote the security of a digital system, however, each day the mechanisms of attack evolve and are integrated, creating separate spheres of combined attacks. In this context, this paper presents an embedded security system (into a SoC system) that has as main goal an integration of the security services. It reaches an improved performance and prevents malicious attacks on systems and networks. The SoC prioritizes the implementation of dedicated functions in hardware as cryptographic algorithms, communication interfaces, among others. In our prototype, initially, the flow control functions and settings are running in software. This article shows the architecture, functionality and performance of the system developed, and we discuss a real implementation in FPGA.

SSDR - Reconfigurable Firewall: Reconfiguration Model Performance

There are a number of techniques and pieces of hardware and software aimed at promoting information security. In the present paper it is presented a security system dynamically reconfigurable in FPGAs. SSDR presents a robust architecture, which enables the implementation of specific and general security policies in order to guarantee services such as confidentiality, authenticity, integrity, availability, access control, and information audit. The main purposes of SSDR include guaranteeing a great security level by reaching time performance acceptable to a conventional computer network, besides a greater flexibility in relation to a configuration of functionalities and to the security policies. In this paper it presented the reconfigurable firewall module, highlighting its architecture, functionalities and performance, as well as focusing on the impact on the reconfigurable time according the model of project adopted.

Performance issues on integration of security services

The integration of security services is an important solution to combat anomalies and attacks on computer systems, assuming that possible difficulties of a security service may be compensated by others. The current works that aim to integrate two or more security services are usually focused on a particular implementation strategy, because the systematic approach to integrated security systems requires the analysis of relations between security data. In our work was proposed and developed a Security Services Integrated Layer (SSIL), consisting of an organization pattern of information security, as well as behavioral models to analyze the occurrence of abnormality identified. The Hidden Markov Model and the proposed solutions as subHMM and Sequential Model allowed the integration of security services based on behavior. In this article we highlight the rates of detection of anomalies and a critical analysis of results.

A VLIW-based cryptoprocessor on FPGAs architecture and performance issues (abstract only)

This work shows a new architecture for a VLIW-based cryptoprocessor, which is implemented on FPGAs. The cryptoprocessor was designed to execute symmetric cryptography algorithms preferentially. To do so, special modules (such SBOX and PERBIT for substitution and permutation operations, respectively) were described in order to increase the performance and simplify the source program. The cryptoprocessor was described using VHDL language, and a prototype was synthesized and implemented in a FPGA Virtex generating occupation statistic data and temporary performance. It is important to note that the special modules which makes the cryptoprocessor different are not specific to a certain cryptography algorithm, and they were projected in order to be preconfigured according to the characteristics of the algorithm to be executed.