Edward Gatt

Comparative study of automatic speech recognition techniques

Over the past decades, extensive research has been carried out on various possible implementations of automatic speech recognition (ASR) systems. The most renowned algorithms in the field of ASR are the mel-frequency cepstral coefficients and the hidden Markov models. However, there are also other methods, such as wavelet-based transforms, artificial neural networks and support vector machines, which are becoming more popular. This review article presents a comparative study on different approaches that were proposed for the task of ASR, and which are widely used nowadays.

FPGA-based autonomous parking of a car-like robot using Fuzzy Logic Control

This paper proposes a hardware solution to the problem of autonomous parking of a car-like robot. The proposed system scans for a valid parking space and performs the necessary manoeuvres to park the robot within that space. Parallel and perpendicular parking is achieved by using a fuzzy logic based system that was developed in a simulation environment and subsequently prototyped on a custom built, car-like robot. Fuzzy logic is being proposed as it provides a fast response with a very small hardware footprint. For optimal efficiency, the system was implemented on an FPGA (Field Programmable Gate Array) resulting in a very cost-effective, yet robust system that could be implemented on a full size vehicle.

Support Vector Machines with the priorities method for speaker independent phoneme recognition

A speaker independent phoneme recognition system, based on Support Vector Machines (SVMs) method was improved by adding a priority scheme to forecast the three most likely phonemes. The system helps improve the obtained recognitions rate. For the phoneme recognition system, four multiclass SVMs methods, the All-at-once, One-against-all, One-against-one, and the Directed Acyclic Graph SVM (DAGSVM), were designed. The One-against-one method performed best, achieving an accuracy of 53.70%. This accuracy was further increased to 75.41%, when the second and third priorities were considered in the priorities method. All tests were carried out on the TIMIT database.

Utilization of MEMS Tunable Inductors in the design of RF voltage-controlled oscillators

This paper presents the concept of using a MEMS piezoelectric actuated tunable inductor in the design of a wideband high performance VCO. Furthermore, a model of the tunable inductor is presented to facilitate the VCO design and simulation. In addition, by means of this model important characteristics of the tunable inductor can be derived enabling a design of the VCO to be superior in phase noise and power consumption to one which makes use of conventional capacitive tuning as indicated by the simulation results.

1.6-GHz low power low phase noise quadrature phase locked loop with on chip DC-DC converter for wide tuning range

This paper presents the design of a 1.6 GHz quadrature phase locked loop for GPS applications, operated with a supply voltage of 1.2 V and dissipating a current of less than 5 mA. It is capable of delivering quadrature locked signals in the range from 1.22 GHz to 1.96 GHz with a phase noise response of less than 115 dBc at an offset of 1 MHz from the carrier. The wide tuning range is obtained using an on-chip regulated DC-DC converter clocked by the reference signal, with negligible effect on phase noise and spurious level of the PLL. The design was made using the STMicroelectronics proprietary 0.13 mum HCMOS9 technology design kit.

Hardware-based support vector machine for phoneme classification

This paper presents the design of a digital hardware implementation based on Support Vector Machines (SVMs), for the task of multi-speaker phoneme recognition. The One-against-one multiclass SVM method, with the Radial Basis Function (RBF) kernel was considered. Furthermore, a priority scheme was also included in the architecture, in order to forecast the three most likely phonemes. The designed system was synthesised on a Xilinx Virtex-II XC2V3000 FPGA, and evaluated with the TIMIT corpus. This phoneme recognition system is intended to be implemented on a dedicated chip, along with the Discrete Wavelet Transforms (DWTs) for feature extraction, to further improve the resultant performance.

Design of a 1.2 V Low Phase Noise 1.6 GHz CMOS Buffered Quadrature Output VCO with Automatic Amplitude Control

This paper presents the design of a low phase noise 1.6 GHz CMOS buffered quadrature output VCO with automatic amplitude control. It is operated with a supply voltage of 1.2 V and dissipates a current of less than 10 mA. It is capable of delivering quadrature locked signals with almost constant amplitude in the range from 1.22 GHz to 1.95 GHz with a phase noise response of less than -115 dBc at an offset of 1 MHz from the carrier. The effect of the automatic amplitude control is shown to improve phase noise at high oscillation frequencies and its noise has a negligible effect on phase noise response, even at low offset frequencies from the carrier. Design guidelines for reducing both the loop noise and the AM-PM conversion factors of the oscillator are also given.

Phoneme classification in hardware implemented neural networks

Among speech researchers, it is widely believed that Hidden Markov Models (HMMs) are the most successful modelling approaches for acoustic events in speech recognition. However, common assumptions limit the classification abilities of HMMs and these can been relaxed by introducing neural networks in the HMM framework. With todays advances in VLSI technology, artificial neural networks (ANNs) can be integrated into a single chip offering adequate circuit complexity required to attain both a high recognition accuracy and an improved learning time. Analogue implementations are considered due to the high processing speeds. The relative performance of different speech coding parameters for use with two different ANN architectures that lend themselves to analogue hardware implementations are investigated. In this case, the dynamic ranges of the different coefficients need to be taken into consideration since they will affect the performance of the analogue chip due to the scaling of the coefficients to voltage signals. The hardware requirements for implementing the two architectures are then discussed.

An analog VLSI time-delay neural network implementation for phoneme recognition

The paper proposes an analog VLSI neural network chip, which can be cascaded in order to develop a time-delay neural network system for phoneme recognition. Backpropagation learning has been adopted to train the network to recognise phoneme frames extracted from the TIMIT database. A prototype chip, implemented using CMOS 2.0 /spl mu/m, double metal, double poly technology is also described together with its specifications.

Discrete wavelet transforms with multiclass SVM for phoneme recognition

A phoneme recognition system based on Discrete Wavelet Transforms (DWT) and Support Vector Machines (SVMs), is designed for multi-speaker continuous speech environments. Phonemes are divided into frames, and the DWTs are adopted, to obtain fixed dimensional feature vectors. For the multiclass SVM, the One-against-one method with the RBF kernel was implemented. To further improve the accuracies obtained, a priority scheme was added, to forecast the three most likely phonemes. After classification, all frames were again re-grouped, in order to evaluate the accuracy of the system according to the substitution, deletion and insertion errors. The percentage correct and accuracy, obtained from the designed phoneme recognition system, were 63.08% and 53.27% respectively. All tests were carried out on the TIMIT database. This phoneme recognition system is intended to be implemented on a dedicated chip, to improve the speed of the software implementation by approximately 100 times.