Edward H. Frank

The SBus: Sun's high performance system bus for RISC workstations

An overview of the design of SBus, Suns SPARCstation 1 memory and input/output (I/O) expansion bus, is presented. In creating the SBus, the foremost goal was that overall system performance should not suffer because of the SBus design. The next most important goal was that I/O devices, including Ethernet and FDDI, be able to rely on the same high-performance, low-latency access to memory that is available to the central processor. Another goal was that it is possible to implement the interface between an I/O device and the SBus in a low-cost CMOS gate array, without having to use external buffers or drivers. A final goal was for the SBus to be the interface for I/O expansion. Raw SBus performance is provided by allowing a system clock of up to 25 MHz, represents a nice balance between ultimate performance and ease of system design and integration when boards are built by different manufacturers.<<ETX>>

SPARCstation 1: beyond the 3M horizon

Not too long ago, the workstation of the future was nicknamed the 3M machine: 1 MIPS, 1 megabyte, and 1 megapixel. The 4M (+ 1 megaflop) machine and 5M (+ 1 megavectors per second) machine weren’t even contemplated. Indeed, thoughts of anything more powerful added three more Ms: megadollars, megaspace, and megawatts. Yet, when Sun introduced SPARC in early 1987, it became apparent that the technology was in hand to build workstations that would by far exceed the goals of the original 3M machine.

Sun's SPARCstation 1: a workstation for the 1990s

The architecture and features of the SPARCstation 1 are described and compared with those of other workstations and PCs of approximately the same cost. The heart of the machine is implemented using seven custom CMOS gate arrays plus a single-chip SPARC integer unit and a single-chip SPARC floating-point unit. The architecture of SPARCstation 1 reflects the use of CMOS technology, especially in the design of the SBus, which is SPARCstation 1s memory and I/O expansion interconnect. As a processing engine, SPARCstation 1 provides the user with 12.5 MIPS, 1.4 MFLOPS, and 64 MB of memory. The SBus provides the means for connecting peripheral devices such as IPI (interprocessor interrupt) drives and FDDI interfaces. The SBus accommodates these devices by having a peak bandwidth of 80 MB/s and a sustained bandwidth in the SPARCstation 1 implementation of approximately 25 to 30 MB/s. An optional graphics accelerator, the GX, can render almost 5 Mvectors/s.<<ETX>>