James Testa

Single in-line memory module

Bus architecture for integrated data and video memory

Method and apparatus for the verification and testing of electrical circuits

Storage cell using low powered/low threshold CMOS pass transistors having reduced charge leakage

High speed electrical signal interconnect structure

Multiple bus architecture for flexible communication among processor modules and memory subsystems and specialized subsystems

Modular circuit board placement system

Dynamic clocked inverter latch with reduced charge leakage

Low power data latch with overdriven clock signals

Protecting cot packaged ICs during wave solder operations