Edward K. F. Lee

A CMOS field-programmable analog array

The design details and test results of a field-programmable analog array (FPAA) prototype chip in 1.2- mu m CMOS are presented. The analog array is based on subthreshold circuit techniques and consists of a collection of a homogeneous configurable analog blocks (CABs) and an interconnection network. Interconnections between CABs and the analog functions to be implemented in each block are defined by a set of configuration bits loaded serially into an onboard shift register by the user. Macromodels are developed for the analog functions in order to simulate various neural network applications on the field-programmable analog array. >

Design of low-voltage bandgap reference using transimpedance amplifier

The minimum supply voltage for implementing a typical bandgap reference is usually over 1.8 V. This minimum is mainly due to the limited input common-mode range of the opamp used in the bandgap reference. In this work, a low-voltage bandgap reference using a transimpedance amplifier that does not have this limitation is proposed and some of the design considerations for the proposed technique are briefly discussed. Based on this technique, a 1.2-V bandgap reference was implemented in a 1.2-/spl mu/m CMOS process (V/sub TN//spl ap/0.53 V and V/sub TP//spl ap/-0.91 V) with bipolar option. The variations of the output voltage over temperature (0/spl deg/C/spl les/T/spl les/100/spl deg/C) were measured to be less than /spl plusmn/1%.

Design of low-power ROM-less direct digital frequency synthesizer using nonlinear digital-to-analog converter

A design technique that uses nonlinear digital-to-analog converter (DAC) for implementing low-power direct digital frequency synthesizer (DDFS) is proposed. The nonlinear DAC is used in place of the ROM look up table for phase-to-sine amplitude conversion and the linear DAC in a conventional DDFS. Since the proposed design technique for DDFS does not require a ROM, significant saving in power dissipation results. The design procedure for implementing the nonlinear DAC is presented. To demonstrate the proposed technique, two quadrature DDFSs, one using nonlinear resistor string DACs and the other using nonlinear current-mode DACs, were implemented. For a 3.3-V supply, the resulting power dissipation for both DDFSs are 4 and 92 mW at a clock rate of 25 MHz and 230 MHz, respectively. For both DDFSs, the spurious free dynamic ranges are over 55 dB for low synthesized frequencies.

Low-voltage analog circuit design based on biased inverting opamp configuration

Analog circuit designs that use inverting opamp configuration can be converted into low-voltage designs by biasing the opamp input common-mode voltage to near one of the supply rails. This is achieved by introducing a current source or a resistor between the opamp negative input terminal and one of the supply rails. Hence, in this technique, opamps with limited input common-mode range can be used. In addition, switches can be incorporated in these circuits to allow a wide range of applications. This technique also allows large input and output signal swings (close to rail-to-rail), even at a very low-voltage supply. To demonstrate the proposed technique, four track-and-hold amplifiers (THAs) and a 10 bit digital-to-analog converter (DAC) have been designed in a conventional 1.2 /spl mu/m CMOS process and tested at a 1 V supply. The DAC consumes less than 0.45 mW and has a maximum throughput of 1 MS/s, with close to rail-to-rail output (0.1-0.9 V). The maximum differential nonlinearity error and integral nonlinearity error were measured to be 1.7 least significant bits (LSBs) and 3.0 LSBs, respectively. Each THA dissipates less than 0.35 mW and achieves a hold mode total harmonic distortion of less than -61 dB for a 100 kHz, 1.4 V/sub p-p/ differential input signal, sampled at a rate of 1 MS/s.

A transconductor-based field-programmable analog array

Field-programmable gate arrays for prototyping digital circuits are a widely endorsed approach for reducing time-to-market. Offering similar advantages, a field-programmable analog array (FPAA) for prototyping continuous-time analog circuits is reported here. Conceptually, a FPAA consists of configurable analog blocks (CABs) and interconnects. The function of each CAB and the connections among CABs are determined by the contents of an on-chip shift register. Different circuits can be instantiated using a FPAA by loading in different configuration bits. This IC strategy offers simplified analog circuit design with the advantages of instant prototyping, programmable topology, programmable parameters, CAD compatibility, and testability.

A Matching Technique for Biphasic Stimulation Pulse

Biphasic pulses are commonly used for neural stimulation. One of the important requirements for biphasic pulses is to maintain charge balance. Since the durations of the cathodic and anodic current pulses are usually set to the same value, the amplitudes of these current pulses are therefore required to be matched. In this paper, a self-calibration technique is proposed to match the amplitudes of the cathodic and anodic current pulses. For pulse amplitude of ~3mA, the amplitude difference between the two pulses can be reduced to less than 2muA after calibration

Field Programmable Logic Gates Using GMR Devices

This paper summarizes the basic methodology for building field programmable logic functions using GMR devices. The size of the gates and the properties of the sense amplifier are a function of the particular GMR technology used, device matching and the magnitude of the sense current available. A test chip is currently in fabrication.

Network sampling in practice: Some second steps

Abstract Network sampling is a potentially invaluable method of studying density of large networks, but its feasibility in practice is largely unknown. Two pretests of a network sampling instrument in a favourable setting (a network with moderate size, high density, and cooperative respondents) with a relatively representative population are reported in this paper. The results indicate that network sampling is indeed viable in such settings. Some suggestions for successful applications are offered.

A Novel Switched-Capacitor Based Field-Programmable Analog Array Architecture

A novel field-programmable analog array (FPAA) architecture based on switched-capacitor techniques is proposed. Each configurable analog block (CAB) in the proposed architecture is an opamp with feedback switches which are controlled by configuration bits. Interconnection networks are used to connect programmable capacitor arrays (PCAs) and the CABs. The routing switches in the interconnection networks not only function as interconnection elements but also switches for the charge transfer required in switched-capacitor circuits. This scheme minimizes the number of connecting switches between CABs and PCAs, thereby, it reduces the settling time of the resultant SC circuits and thus achieving high speed operation. The architecture is highly flexible and provides for the implementation of various A/D and D/A converters when the FPAA is connected with external digital circuits or field-programmable gate arrays (FPGAs).

A 2 GHz VCO with process and temperature compensation

A CMOS VCO with inherent compensation for temperature and process variations is presented. In the new design, the VCO input control is divided into two parts. One is controlled by a temperature and process compensation bias circuit and the other is controlled by an external input. A phase locked loop is used as the temperature and process compensation bias circuit. Two ideally identical VCOs are used. The control voltage of the VCO in the PLL will track the temperature and process variations. This control voltage is fed back to the VCO outside the loop. Simulation results show the total variation in the VCO frequency over a 100/spl deg/C temperature range and over the fast and slow process corners is about /spl plusmn/1.7%. This is a reduction of in excess of a factor of 12 when compare to a conventional VCO design based on the same delay stage.