Marwan M. Hassoun

A hierarchical network approach to symbolic analysis of large-scale networks

A hierarchical approach to the problem of symbolic circuit analysis of large-scale circuits is presented in this paper. The methodology has been implemented in a computer program called SCAPP (Symbolic Circuit Analysis Program with Partitioning). The method solves the problem by utilizing a hierarchical network approach and the sequence of expressions concept rather than a topological approach and the single expression idea which have dominated symbolic analysis in the past. The result is a linear growth (for real circuits) in the number of terms in the symbolic solutions for the network approach versus the exponential growth exhibited by traditional methods. The analysis methodology uses a Reduced Modified Nodal Analysis (RMNA) technique that allows the characterization of symbolic networks in terms of only a small subset of the network variables (external variables). The analysis algorithm is most efficient when network partitioning is used. Partitioning results in a reduction in the number of terms in the symbolic solutions. >

A new network approach to symbolic simulation of large-scale networks

A new approach to the problem of symbolic circuit analysis of large-scale circuits is presented. The methodology has been implemented in a computer program called SCAPP (symbolic circuit analysis program with partitioning). The method solves the problem by utilizing a hierarchical network approach and the sequence of expressions concept rather than a topological approach and the single expression idea which have dominated symbolic analysis in the past. The result is a linear growth in the number of terms in the symbolic solutions for the network approach versus the exponential growth exhibited by traditional methods. The analysis methodology introduces the concept of the RMNA (reduced modified nodal analysis) matrix. This allows the characterization of symbolic networks in terms of only a small subset of the network variables (external variables) rather than the complete set of variables. The analysis algorithm is most efficient when network partitioning is used. Partitioning results in a reduction in the number of terms in the symbolic solutions.<<ETX>>

Symbolic analysis of large-scale networks using a hierarchical signal flowgraph approach

This paper presents an approach suitable for the symbolic analysis of large-scale active networks. The method depends on the partitioning of the network into smaller networks which are then symbolically analyzed noniteratively using the Masons signal flowgraph models of each partition. The resulting solutions, which are reduced signal flowgraphs (transfer functions) for the subnetworks are then hierarchically combined to produce the final solution or solutions (transfer functions) for the entire system. The advantage of such an approach is the reduction in the number of symbolic terms compared to the conventional approaches, and the ability to analyze hybrid systems consisting of electrical and nonelectrical parts. The result of the analysis is a series of equations that have an upward hierarchical dependency on each other.

Field Programmable Logic Gates Using GMR Devices

This paper summarizes the basic methodology for building field programmable logic functions using GMR devices. The size of the gates and the properties of the sense amplifier are a function of the particular GMR technology used, device matching and the magnitude of the sense current available. A test chip is currently in fabrication.

Time-interleaved A/D converter with channel randomization

Gain errors and offsets in time-interleaved structure A/D converters result in distortion in the output spectrum. To reduce these effects, a new method utilizing randomization technique is proposed. Simulation results show that the distortion level caused by gain errors and offsets was lowered. One of the advantages of this proposed method is that it requires low hardware cost to implement when compared to other auto-calibrating methods.

Hierarchical symbolic analysis of large-scale systems using a Mason's signal flow graph model

The author presents an approach to the symbolic analysis of large-scale systems. The method depends on the partitioning of the system into smaller subsystems which are then symbolically analyzed individually and non-iteratively using Masons signal flow graph models of these smaller subsystems. The resulting solutions which are reduced signal flow graphs (transfer functions) for the subsystems are then hierarchically combined to produce the final solution or solutions (transfer functions) for the whole system. The advantage of such an approach is the tremendous reduction in the number of symbolic terms compared to the conventional approaches that can only handle very small circuits. The result of the analysis is a series of equations that have an upward hierarchical dependency on each other.<<ETX>>

An efficient partitioning algorithm for large-scale circuits

A parallel circuit-partitioning algorithm aimed at minimizing the number of tearing nodes between subcircuits, the size of each subcircuit, or both, is presented. The algorithm is most suitable for circuit-simulation problems. It is currently implemented in a symbolic circuit simulator (SCAPP). The algorithm depends on the exploration of the coupling between the modified fundamental loops of the circuit. It recursively performs a hierarchical binary partitioning on the circuit and its subcircuits based on the concepts of loop index, tearing index, and branch index. Experimental results show the algorithm reaching optimum or better near-optimal solutions to problems for which existing algorithms failed or produced worse solutions.<<ETX>>

An algorithm for simulating power/ground networks using Pade approximants and its symbolic implementation

This paper presents an event-driven algorithm and its symbolic implementation for the analysis of power and ground (P/G) bus networks. The algorithm uses frequency-domain techniques and moment matching approaches based on Pade approximants to estimate the transfer function at each node in the P/G network. Afterwards, the transient waveforms are extracted for each node. The process requires repetitive simulation of a linear and time-variant (from one time event to the next) circuit model for the P/G network which is the reason a symbolic implementation was produced. The P/G network is modeled by a hierarchical combination of mesh and tree structures that are composed of a collection of RC-/spl pi/-segments and pulldown (or pullup) switches. The switches are symbolically represented by Boolean variables and a compiled symbolic code is generated only once for each P/G network. The transient waveforms are then produced by repetitive evaluation of the symbolic output. The results show that the symbolic implementation is an order of magnitude faster, with reasonably good accuracy, than using a traditional analog circuit simulator like SPICE.

A 9-b 40-MSample/s reconfigurable pipeline analog-to-digital converter

In this paper, a reconfigurable pipeline analog-to-digital converter (ADC) architecture is proposed. Based on dynamic performance measurements, the best performance configuration will be chosen from a collection of possible configurations. A 40-MSample/s 9-b reconfigurable pipeline ADC is designed and implemented in Taiwan Semiconductor Manufacturing Corporations (TSMCs) 0.25-/spl mu/m single-poly CMOS digital process. The chip is measured for all the configurations under different temperatures to prove the reconfiguration will provide significant effective number of bits (ENOB) improvement among the set of configurations. The active area of the design is 5.9 mm/sup 2/. The power consumption is 425 mW.

A high speed fully differential CMOS opamp

A high-speed fully differential folded cascode operational amplifier is presented. The operational amplifier uses fully differential boosting amplifiers to increase the open loop gain of the opamp. The opamp has a CMFB circuit that is made of a switched capacitor circuit and a continuous time CMFB circuit. The boosting amplifiers have continuous time CMFBs. The opamp is designed in TSMC 0.25 u digital CMOS process with 2.5 V power supply and achieved a dc gain of 81 dB with a 680 MHz unity gain frequency and 30 mW power consumption.