Edwin C. Becerra-Alvarez

Adaptive CMOS analog circuits for 4G mobile terminals-Review and state-of-the-art survey

The fourth-generation (4G) of cellular terminals will integrate the services provided by previous generations second-generation/third-generation (2G/3G) with other applications like global positioning system (GPS), digital video broadcasting (DVB) and wireless networks, covering metropolitan (IEEE 802.16), local (IEEE 802.11) and personal (IEEE 802.15) areas. This new generation of hand-held wireless devices, also named always-best-connected systems, will require low-power and low-cost multi-standard chips, capable of operating over different co-existing communication protocols, signal conditions, battery status, etc. Moreover, the efficient implementation of these chipsets will demand for reconfigurable radio frequency (RF) and mixed-signal circuits that can adapt to the large number of specifications with minimum power dissipation at the lowest cost. Nanometer CMOS processes are expected to be the base technologies to develop 4G systems, assuring mass production at low cost through increased integration levels and extensive use of digital signal processing. However, the integration in standard CMOS of increasingly complex analog/RF parts imposes a number of challenges and trade-offs that make their design critical. These challenges are addressed in this paper through a comprehensive revision of the state-of-the-art on transceiver architectures, building blocks and design trade-offs of reconfigurable and adaptive CMOS RF and mixed-signal circuits for emerging 4G systems.

Design of a 1-V 90-nm CMOS folded cascode LNA for multi-standard applications

This paper analyses the use of folded cascode Low Noise Amplifiers (LNAs) for the implementation of multi-standard wireless transceivers. The proposed LNA consists of a two-stage topology made up of a folded cascode and simple-stage amplifiers that use NMOS-varactor based tuning networks to make the operating frequency continuously programmable. The circuit has been designed and implemented in a 90-nm CMOS technology in order to cope with the requirements of GSM, WCDMA, Bluetooth and WLAN (IEEE 802.11b/g) standards. Practical design issues are analysed, considering the effect of circuit parasitics associated to both the chip package and integrated inductors, capacitors and varactors; as well as technology parameter deviations. The circuit design is optimized using genetic algorithms to achieve the required specifications with adaptive power consumption. Layout-extracted simulation results demonstrate a correct operation of the proposed circuit, showing a continuous tuning of Noise Figure (NF) and S-parameters within the 1.85–2.48GHz band, featuring NF<3.8dB, S21 >12dB and IIP3> −12dBm, with an adaptive power dissipation between 13.3mW and 23.1mW from a 1-V supply voltage.

Adaptive CMOS LNAs for beyond-3G RF receivers - A multi-standard GSM/WCDMA/BT/WLAN case study

This paper reviews the main circuit strategies reported so far for the implementation of multi-standard Low-Noise Amplifiers (LNAs) and presents a reconfigurable and adaptive LNA intended for Beyond-3G RF hand-held devices. The circuit, designed and implemented in a 90-nm CMOS technology, combines a reduced number of inductors with PMOS-varactors and programmable load to adapt its performance to different standard specifications with optimized power consumption. As a case study, the LNA has been designed to cope with the requirements of four standards: GSM, WCDMA, Bluetooth (BT) and WLAN (IEEE 802.11b-g). Simulation results, including technology and packaging parasitics, demonstrate correct operation of the circuit for all the standards under study, featuring NF≪2.8dB, S21≫13.3dB and IIP3≫10.9dBm over a 1.85–2.48GHz band, with an adaptive power consumption between 17.4mW and 21.7mW from a 1-V supply voltage.

Flexible CMOS low-noise amplifiers for beyond-3G wireless hand-held devices

This paper explores the use of reconfigurable Low-Noise Amplifiers (LNAs) for the implementation of CMOS Radio Frequency (RF) front-ends in the next generation of multi-standard wireless transceivers. Main circuit strategies reported so far for multi-standard LNAs are reviewed and a novel flexible LNA intended for Beyond-3G RF hand-held terminals is presented. The proposed LNA circuit consists of a two-stage topology that combines inductive-source degeneration with PMOS-varactor based tuning network and a programmable load to adapt its performance to different standard specifications without penalizing the circuit noise and with a reduced number of inductors as compared to previous reported reconfigurable LNAs. The circuit has been designed in a 90-nm CMOS technology to cope with the requirements of the GSM, WCDMA, Bluetooth and WLAN (IEEE 802.11b-g) standards. Simulation results, including technology and packaging parasitics, demonstrate correct operation of the circuit for all the standards under study, featuring NF<2.8dB, S21>13.3dB and IIP3>10.9dBm, over a 1.85GHz-2.4GHz band, with an adaptive power consumption between 17mW and 22mW from a 1-V supply voltage. Preliminary experimental measurements are included, showing a correct reconfiguration operation within the operation band.

Methodology to improve the model of series inductance in cmos integrated inductors

Abstract This paper presents a systematic optimization methodology to achieve an accurate estimation of series inductance of inductors implemented in standard CMOS technologies. Proposed method is based on an optimization procedure which aims to obtain adjustment factors associated to main physical inductor characteristics, allowing to estimate more accurate series inductance values that can be used in design stage. Experimental measurements of diverse square inductor geometries are shown and compared with previous approaches in order to demonstrate and validate presented approach

Using Arduino and on-chip serial-to-parallel register to test widely-programmable ADCs

This paper presents an experimental set-up that combines on-chip digital techniques with off-chip Arduino-based hardware to simplify the test of widely-programmable analog-to-digital converters. The presented methodology is specially intended for analog and mixed-signal circuits which require a large number of digital signals to reconfigure their performance to different electrical specifications, environment signal conditions, battery status, etc. To this end, a serial-to-parallel register is implemented on chip in order to generate the required number of digital control signals from an input serial data provided offchip. Such serial data can be generated by using an Arduino-based hardware set-up, which can be easily programmed in MATLAB, with no additional test instruments required. As an application, the proposed method is applied to the experimental characterization of a fourth-order band-pass continuous-time ΣΔ modulator, integrated in a 65-nm CMOS technology, which can digitize signals placed at programmable carrier frequencies for software defined radio1.

A silicon-based 2.4GHz fully-differential LC-VCO: A design methodology proposal

This paper presents a methodology to design voltage controlled oscillators. The usefulness of the design proposal is shown by designing a LC oscillator in a 130nm CMOS technology, intended for Bluetooth/Zigbee applications. From simulations results, when temperature varies from 0 to 100°C, power consumption ranging from 3.1mW to 3.81mW is achieved. At 3.4mW of power consumption, a phase noise of -119 dBc/Hz was obtained. In this proposal, NMOS varactors achieve a tuning range of 150MHz.

EKV-based method for biasing CMOS analog cells using mUltiple-Inputs Floating Gate MOSFETs

A MATLAB method is introduced for biasing CMOS analog cells operating in weak inversion region and based on the Multiple-Input Floating Gate MOS Transistor. Despite SPICE language is a widely accepted tool to design CMOS analog cells, it has some problems to simulate circuits based on the Multiple-Input Floating Gate Transistor since floating nodes appear giving rise to problems of convergence and initialization. The strategy introduced here is implemented entirely in the MATLAB environment and based on the EKV transistor model. By way of example, the method is discussed using an operational amplifier. Furthermore, this technique facilitates both the bias and analysis because the MATLAB code can be easily modified to improve the model and reduce the error between simulation and measurement results. This technique may be useful for students interested in designing weak inversion analog cells using the floating gate transisor but can also be helpful for professional designers.

Design considerations and experimental results of continuously-tuned reconfigurable CMOS LNAs

This paper analyses the use of continuously-tuned Low Noise Amplifiers (LNAs) for the implementation of the next generation of software-defined radio receivers. Two LNA circuits are discussed. One is based on a folded cascode stage and the other one consists on a two-stage inductively degenerated common-source configuration. Both LNAs - designed and implemented in a 1-V 90-nm CMOS technology - employ MOS-varactor based tuning networks to make the operating frequency continuously programmable within the band of interest, targeting the requirements of GSM, UMTS, Bluetooth and WLAN standards, as well as any other operation mode in between. Practical design issues are presented, considering the effect of circuit parasitics associated to both the chip package and integrated inductors, capacitors and varactors; as well as technology parameter deviations. Experimental measurements demonstrate a correct operation of the circuits, showing a continuous tuning of Noise Figure (NF) and S-parameters within a 1.75–2.48GHz band, featuring NF&#60;3.7dB, S21 >19.6dB and IIP3> −9.8dBm in a frequency range of 1.75–2.23GHz.1