F. Sandoval-Ibarra

Adaptive CMOS LNAs for beyond-3G RF receivers - A multi-standard GSM/WCDMA/BT/WLAN case study

This paper reviews the main circuit strategies reported so far for the implementation of multi-standard Low-Noise Amplifiers (LNAs) and presents a reconfigurable and adaptive LNA intended for Beyond-3G RF hand-held devices. The circuit, designed and implemented in a 90-nm CMOS technology, combines a reduced number of inductors with PMOS-varactors and programmable load to adapt its performance to different standard specifications with optimized power consumption. As a case study, the LNA has been designed to cope with the requirements of four standards: GSM, WCDMA, Bluetooth (BT) and WLAN (IEEE 802.11b-g). Simulation results, including technology and packaging parasitics, demonstrate correct operation of the circuit for all the standards under study, featuring NF≪2.8dB, S21≫13.3dB and IIP3≫10.9dBm over a 1.85–2.48GHz band, with an adaptive power consumption between 17.4mW and 21.7mW from a 1-V supply voltage.

Behavioral modelling of a 4 th order LP ΣΔ modulator-towards the design of a hybrid proposal

Hybrid ΣΔ modulator has the property of take advantage of the capabilities of CT and DT architectures and is thus very effective in the cascade approach. In this paper, we show the behavioral simulation of ΣΔ modulators in SIMSIDES. A set of experiments based on models for analyzing the overall performance of SC ΣΔ modulators were used in order to translate design considerations into a set of values such that the design at transistor level be established by the desired performance of the proposed architecture. This design methodology is not the most accurate but it allows the designer to get a general comprehension of the system under design, a comprehension at the highest level of abstraction. The system under study is a cascade 4th order hybrid ΣΔ modulator, from which the second stage is a 2nd order Low-Pass (LP) DT ΣΔ modulator. The ideal behavioral performance of the DT modulator is used as vehicle to show how non-idealities must be taken into account, and also how to translate design considerations into a set of physical values for designing building blocks at transistor level.

Implementation of SoC Based Real-Time Electromagnetic Transient Simulator

Real-time electromagnetic transient simulators are important tools in the design stage of new control and protection systems for power systems. Real-time simulators are used to test and stress new devices under similar conditions that the device will deal with in a real network with the purpose of finding errors and bugs in the design. The computation of an electromagnetic transient is complex and computationally demanding, due to features such as the speed of the phenomenon, the size of the network, and the presence of time variant and nonlinear elements in the network. In this work, the development of a SoC based real-time and also offline electromagnetic transient simulator is presented. In the design, the required performance is met from two sides, (a) using a technique to split the power system into smaller subsystems, which allows parallelizing the algorithm, and (b) with specialized and parallel hardware designed to boost the solution flow. The results of this work have shown that for the proposed case studies, based on a balanced distribution of the node of subsystems, the proposed approach has decreased the total simulation time by up to 99 times compared with the classical approach running on a single high performance 32-bit embedded processor ARM-Cortex A9.

Non-idealities in analog circuits design: What does it really mean?

The aim of this contribution is to show why sources of non-idealities are actually a concept of reason in order to define tradeoffs in the design of analog circuits. A tradeoff is commonly picked up from an analytical design-model, which tries to explain a given phenomenon under study by using physical theories underlying the role of non-idealities in the design of accurate analog-circuits. Since accuracy is commonly used as a measure rule for minimizing the unwanted effect of non-idealities on the circuit performance, this paper underlines that non-idealities reported in open literature shown that any analog circuit is designed in a custom way, in which just some non-idealities are minimized in order to fulfill specific design specifications, i.e. sources of non-idealities do not necessarily include all existing ones but just those affecting -according the experience of the designer - the circuits performance. Thus, what non-idealities have to be minimized in an analog circuit design is a question usually answered by reachable tradeoffs. This paper addresses difficulties (i.e. open problems) about silicon-based analog circuit design. So, analog design is not art, but an engineering activity supported in physical theories. Analog design demands not only accurate design models, and suitable simulation tools, but also a well-defined design methodology, elsewhere trial-and-error practices force to the analog-circuit designer to include substantial design margin and risk yield loss, and also provide little design knowledge.

Flexible CMOS low-noise amplifiers for beyond-3G wireless hand-held devices

This paper explores the use of reconfigurable Low-Noise Amplifiers (LNAs) for the implementation of CMOS Radio Frequency (RF) front-ends in the next generation of multi-standard wireless transceivers. Main circuit strategies reported so far for multi-standard LNAs are reviewed and a novel flexible LNA intended for Beyond-3G RF hand-held terminals is presented. The proposed LNA circuit consists of a two-stage topology that combines inductive-source degeneration with PMOS-varactor based tuning network and a programmable load to adapt its performance to different standard specifications without penalizing the circuit noise and with a reduced number of inductors as compared to previous reported reconfigurable LNAs. The circuit has been designed in a 90-nm CMOS technology to cope with the requirements of the GSM, WCDMA, Bluetooth and WLAN (IEEE 802.11b-g) standards. Simulation results, including technology and packaging parasitics, demonstrate correct operation of the circuit for all the standards under study, featuring NF<2.8dB, S21>13.3dB and IIP3>10.9dBm, over a 1.85GHz-2.4GHz band, with an adaptive power consumption between 17mW and 22mW from a 1-V supply voltage. Preliminary experimental measurements are included, showing a correct reconfiguration operation within the operation band.

Design of a 0.18μm Low-Voltage Switched-Current ΣΔ Modulator for Multistandard Communication Systems

This paper presents a 1.8-V, 0.18 μm CMOS reconfigurable switched-current ΣΔ modulator for multistandard (GSM, Bluetooth, WCDMA) telecom systems. The modulator topology is an expandable cascade architecture which can be reconfigured both at the architecture level and at the circuit level in order to adapt the modulator performance to the different standards with adjustable power consumption. For this purpose, programmable Class AB memory-cell arrays are used to implement the modulator loop filter. Transistor- level simulations are shown that demonstrate correct operation for all standards, featuring 12-bit, 11-bit and 7.8-bit dynamic range within 200-kHz, 1-MHz and 3.8-MHz bandwidth, respectively.

American Sign Language Alphabet Recognition Using a Neuromorphic Sensor and an Artificial Neural Network

This paper reports the design and analysis of an American Sign Language (ASL) alphabet translation system implemented in hardware using a Field-Programmable Gate Array. The system process consists of three stages, the first being the communication with the neuromorphic camera (also called Dynamic Vision Sensor, DVS) sensor using the Universal Serial Bus protocol. The feature extraction of the events generated by the DVS is the second part of the process, consisting of a presentation of the digital image processing algorithms developed in software, which aim to reduce redundant information and prepare the data for the third stage. The last stage of the system process is the classification of the ASL alphabet, achieved with a single artificial neural network implemented in digital hardware for higher speed. The overall result is the development of a classification system using the ASL signs contour, fully implemented in a reconfigurable device. The experimental results consist of a comparative analysis of the recognition rate among the alphabet signs using the neuromorphic camera in order to prove the proper operation of the digital image processing algorithms. In the experiments performed with 720 samples of 24 signs, a recognition accuracy of 79.58% was obtained.

Analysis of an OTA/output stage for a SC integrator in a Hybrid ΣΔ Modulator

In this paper SIMSIDES-based (Simulink-based Sigma Delta Simulator) high level simulation of a 4th order Hybrid ΣΔ Modulator was carried out to find the performance requirements of several Analog Building Blocks (ABB). Once the requirements have been defined, the next step is to design each ABB at the transistor level. One of them, a fully differential OTA, was sized through a Design of Experiments (DOE) by assessing the required performance of a 2nd order Switched Capacitor (SC) ΣΔ Modulator. By using this design strategy how to translate performance requirements into a set of values -at transistor level- is established by the desired performance of the architecture, i.e. the 4th order Hybrid ΣΔ Modulator. In line with this design strategy, a CFCFC (Complementary Folded Cascode Feedforward Compensated) OTA was designed with design rules of a standard 130nm CMOS process. However, since charging time (τch) is a design requirement deduced from the desired performance of the DT modulator, an output stage (voltage follower) was designed in order to obtain an output resistance of a few ohms, so that charging time satisfies τch<2ns. CADENCE simulation results allow us to highlight that the accuracy of mathematical models, obtained from small-signal analysis (OTA+output stage), enhance high level analysis and minimize simulation time.

Real time hardware accelerator for image filtering

The image processing nowadays is a field in development, many image filtering algorithms are tested every day; however, the main hurdles to overcome are the difficulty of implementation or the time response in a general purpose processors. When the amount of data is too big, a specific hardware accelerator is required because a software implementation or a generic processor is not fast enough to respond in real time. In this paper optimal hardware implementation is proposed for extracting edges and noise reduction of an image in real time. Furthermore, the hardware configuration is flexible with the ability to select between power and area optimization or speed and performance. The results of algorithms implementation are reported.

Design considerations and experimental results of continuously-tuned reconfigurable CMOS LNAs

This paper analyses the use of continuously-tuned Low Noise Amplifiers (LNAs) for the implementation of the next generation of software-defined radio receivers. Two LNA circuits are discussed. One is based on a folded cascode stage and the other one consists on a two-stage inductively degenerated common-source configuration. Both LNAs - designed and implemented in a 1-V 90-nm CMOS technology - employ MOS-varactor based tuning networks to make the operating frequency continuously programmable within the band of interest, targeting the requirements of GSM, UMTS, Bluetooth and WLAN standards, as well as any other operation mode in between. Practical design issues are presented, considering the effect of circuit parasitics associated to both the chip package and integrated inductors, capacitors and varactors; as well as technology parameter deviations. Experimental measurements demonstrate a correct operation of the circuits, showing a continuous tuning of Noise Figure (NF) and S-parameters within a 1.75–2.48GHz band, featuring NF&#60;3.7dB, S21 >19.6dB and IIP3> −9.8dBm in a frequency range of 1.75–2.23GHz.1