Edwin Naroska

A service gateway for networked sensor systems

An emerging area in ubiquitous computing is networked sensor systems. The typical approach is to connect sensor-actuator devices using classic network infrastructures at a low level. These networks can serve as infrastructures to dynamically integrate, sensors and actuators into complex interactive systems while providing convenient services and interfaces to users. A prominent scenario for ubiquitous computing and ad hoc networking is an in-house environment using smart sensor system. Shaman, an extendable Java-based service gateway for networked sensor systems, integrates small network-attached sensor-actuator modules (SAMs) into heterogeneous, high-level networking communities. The system unburdens its connected SAMs by transferring functionality from the SAMs to the gateway.

On an on-line scheduling problem for parallel jobs

This paper addresses the non-preemptive on-line scheduling of parallel jobs. In particular we assume that the release dates and the processing times of the jobs are unknown. It is already known that for this problem Garey and Grahams list scheduling algorithm achieves the competitive factor 2−1m for the makespan if m identical machines are available and if each job requires only a single machine for processing. Here, we show that the same factor also holds in the case of parallel jobs.

A data puncturing IR-scheme for type-II hybrid ARQ protocols using LDPC codes

We present a data puncturing (DP) type-II hybrid ARQ protocol with low-density parity-check (LDPC) codes. Incremental redundancy is created from punctured versions of the original data using the same encoder/decoder hardware. Thus, parts of the initially received data can be gradually improved until successful decoding of the entire code is possible. In comparison to a rate-compatible (RC) type-II hybrid ARQ scheme, a much higher rate LDPC code can be used for encoding/decoding. The proposed approach combines low hardware overhead with high worst case decoding performance. This combination has not been achieved with other schemes so far. The principle is therefore especially suitable for mobile applications. Further, performance analysis shows that the proposed scheme significantly outperforms a type-III HARQ protocol with diversity combining in terms of data throughput.

On optimizing power and crosstalk for bus coupling capacitance using genetic algorithms

The use of deep submicron (DSM) technology increases the capacitive coupling between adjacent wires leading to severe crosstalk noise, which causes power dissipation and may also lead to malfunction of the chip. In this paper, we present a technique that reduces crosstalk noise on buses based on profiling the switching behavior. Based on this profiling information, we apply an architecture that encodes pairs of bus wires, permutes the wires and assigns an inversion level to each wire in order to optimize for power and noise. The architecture configuration is obtained using a genetic algorithm. Unlike previous bus encoding approaches, crosstalk reduction can be balanced with delay and area overhead. Moreover, if delay (or area) is most critical, our architecture can be tailored to add nearly no overhead to the design. For our experiments, we used processor traces obtained from 12 SPEC2000 benchmark programs. The results show that our approach can reduce crosstalk up to 60% on address buses and up to 54% on instruction buses.

A New Scheduling Method for Parallel Discrete-Event Simulation

In this paper we introduce a new conservative and non blocking algorithm for discrete event simulation on parallel computers with distributed memory. The new approach, called critical process first (CPF) algorithm, is especially well suited for simulating complex VLSI designs consisting of many logical processes. The algorithm avoids deadlocks by repeatedly sending lookahead information about critical processes to other computation nodes. Processes are called critical if they may directly influence processes of another computation node. To hide the communication latency of the parallel computer the CPF method gives priority to the execution of events which may affect critical processes. Simulation results show the superiority of the CPF algorithm over approaches without priority handling.

Conservative Parallel Simulation of a Large Number of Processes

In this paper we evaluate parallel simulation based on conservative parallel discrete-event simulation algorithtms. We focus on optimization techniques for simulation models consisting of a large set of elements or processes. One of the main problems during simulation of these large models is the synchronization of elements located on the same processor. While advanced algo rithms are often very time consuming, simple methods fail to exploit the parallelism within the model. Here we describe methods which exploit the parallelism within a model while adding only moderate overhead to the simulation. Finally, we present some simulation results based on our methods.

Simultaneously optimizing crosstalk and power for instruction bus coupling capacitance using wire pairing

The use of deep-submicrometer (DSM) technology increases the capacitive coupling between adjacent wires leading to severe crosstalk noise, which causes power dissipation and may also lead to malfunction of a chip. In this paper, we present a technique that reduces crosstalk noise on instruction buses. While previous research focuses primarily on address buses, little work can be applied efficiently to instruction buses. This is due to the complex transition behavior of instruction streams. Based on instruction sequence profiling, we exploit an architecture that encodes pairs of bus wires and permute them in order to optimize power and noise. A close to optimal architecture configuration is obtained using a genetic algorithm. Unlike previous bus encoding approaches, crosstalk reduction can be balanced with delay and area overhead. Moreover, if delay (or area) is most critical, our architecture can be tailored to add nearly no overhead to the design. For our experiments, we used instruction bus traces obtained from 12 SPEC2000 benchmark programs. The results show that our approach can reduce crosstalk up to 50.79% and power consumption up to 55% on instruction buses.

Sindrion: a prototype system for low-power wireless control networks

We present a system architecture called Sindrion which allows us to create a cheap, energy-efficient, wireless control network to integrate small embedded sensors and actuators into one of the most established middleware platforms for distributed semantic services, namely universal plug and play (UPnP). To meet rigid constraints regarding cost and power consumption, complex data processing is sourced out from the sensor or actuator nodes to dedicated computing terminals, which establish a proxy in the UPnP network.

A hardware-efficient color segmentation algorithm for face detection

This paper develops a hardware-efficient color segmentation algorithm that is especially suitable to implement on hardware for face detection. Since the modulized design is adopted in the proposed algorithm without floating-point operation, the computational cost is directly reduced for hardware design. The proposed algorithm consists of a color space modeling module and a feature enhancement module. The significant skin/lip color features distribution can be accurately detected by using our proposed algorithm to facilitate the face detection. The proposed algorithm was implemented on a field-programmable gate array (FPGA) system for verifying its efficiency. Compared with other state-of-the-art algorithms, the proposed algorithm can significantly decrease the computational cost of the hardware implementation by using color segmentation instead of the overall analysis of the color distribution. Experimental results have verified that our proposed FPGA system occupies only 3,202 logic cells, or about five times less than the current comparable FPGA system with better detection rate.

Bipartitioning and encoding in low-power pipelined circuits

In this article, we present a bipartition dual-encoding architecture for low-power pipelined circuits. We exploit the bipartition approach as well as encoding techniques to reduce power dissipation not only of combinational logic blocks but also of the pipeline registers. Based on Shannon expansion, we partition a given circuit into two subcircuits such that the number of different outputs of both subcircuits are reduced, and then encode the output of both subcircuits to minimize the Hamming distance for transitions with a high switching probability. We measure the benefits of four different combinational bipartitioning and encoding architectures for comparison. The transistor-level simulation results show that bipartition dual-encoding can effectively reduce power by 72.7&percent; for the pipeline registers and 27.1&percent; for the total power consumption on average. To the best of our knowledge, it is the first work that presents an in-depth study on bipartition and encoding techniques to optimize power for pipelined circuits.