Edwin Roks

The double-sided floating-surface detector: an enhanced charge-detection architecture for CCD image sensors

A new high speed, low noise, non-destructive charge detector, called the Double-Sided Floating-Surface Detector (DSFSD), which is fabricated in a standard CCD image sensor process, is reported. This detector can be integrated in CCD image sensors and is capable of detecting large charge packets at very low noise levels. Typical values are 5-8 noise electrons (within 5 MHz) for a charge packet size of 100,000 to 250,000 electrons. The detector is used as the first MOS transistor in a three-stage source-follower configuration with a bandwidth of 150 MHz. The performance of the detector is calculated using a new, simple, model and experimentally verified.

A 2/3" 2-M pixel progressive scan FT-CCD for digital still camera applications

The first 2M-pixel CCD image sensor especially developed for digital still camera applications is presented. The sensor can be operated in various modes, to best suit the camera requirements. High-quality full resolution images are obtained using the cameras mechanical shutter. A variety of subsampled color images of reduced vertical resolution can be generated by simply changing the pulse pattern, allowing, e.g. real-time preview mode on the cameras LCD display, or fast auto-focus mode. The sensor output amplifier combines low noise and excellent linearity with a high conversion factor.

An mK/spl times/nK bouwblok CCD image sensor family. II. Characterization

For pt. I see ibid., vol. 49, no. 3, p. 361-69 (2002). This paper characterizes the performance of four sensors from the bouwblok family. The original design meets the key original design goals, including the maximum packet size Q/sub max/, readout speed, antiblooming protection, and optical performance. Three-level vertical clocks are used to reach more than 12-bits linear dynamic range at 60/spl deg/C, and the binning capacity is limited at the floating diffusion and in the horizontal register. The dark current is low for a modern non-MPP (multiphase pinned) technology (0.3 nA/cm/sup 2/). The performance of the design is consistent (for identical clocking conditions at the pixel) across all members of the family.

The hole role

The importance of holes in solid-state image sensors is described. Todays success of digital imaging is based on the positive effect of an accumulation layer that reduces the interface-related dark current and dark current fixed-pattern noise. This superb imaging feature is applied in CCD as well as in CMOS devices, in consumer as well as in professional equipment. Holes are not only used to improve the dark performance of imagers, other examples are fixing electrostatic potentials, creating gate structures, draining photon-generated charges and constructing output-amplifier stages

Characterization of surface- and buried-channel detection transistors for CCD on-chip amplifiers

Low noise floating-diffusion amplifiers, made in double and single layer membrane poly-Si technology, are characterized including scaling rules for the 1/f noise, thermal noise, 3 dB bandwidth and conversion gain. A comparison is made between buried- and surface-channel detection node transistors for various channel widths, lengths, and bias currents. A new method for measuring the total detection node capacitance is used. The results are modeled using a noise model that includes shot noise from hot-electron effects.

A twin-channel (p and n) FT-CCD imager with cross-antiblooming

A new class of Frame-Transfer CCD image sensors is presented, which is based on the use of both electrons and holes as information carriers and has a novel cross-antiblooming structure for overexposure protection. The device consists of alternate columns of p- and n-channel CCDs, which form two separately operating p and n imagers. This concept is based on the use of the n channel as a channel isolator for the p channel and vice versa and has five advantages. First, the complete area of the image section is active because no light-insensitive channel stop area is required. Secondly, both generated carriers electrons and holes can be stored and transported simultaneously. Thirdly, in a typical four-phase clocking system the electron pixels and the hole pixels are separated by half a pixel pitch in both the vertical and horizontal directions, which improves the pixel-packing density and aliasing suppression. Fourthly, the pattern also forms a line-quincunx sampling grid, which offers many advantages for signal processing, especially as the p- and n-output signals are simultaneously available. Finally, this pixel configuration is also ideally suitable for realizing a progressive-scan imager and a color imager.

Real-time imaging with mega-pixel charge-coupled devices

A technology is described which allows the application of real-time imaging in combination with mega-pixel CCDs. This technology is based on the following characteristics: high-speed transport of the video information through the parallel CCDs in the imaging section, very high-speed transport of the charge packets through the serial section of the devices, and high- speed conversion of the electrons to a measurable voltage by the output amplifier. Key competencies to comply with these requirements are: low-resistive CCD gates, low- capacitance CCD gates and high bandwidth and low noise floor output stages.