Ehud Tirosh

Dual-sensor technology for high-speed detection of 0.1-μm defects

Advanced semiconductor devices, such as 64 Mbit DItAMs, are characterized by increased circuit density, shrinking geometries (0.35 micron design rules) higher circuit complexity and an increasing number of mask levels used for device production. Successful manufacturing of such devices requires not only the decrease of the total number of defects, but also the decrease of the number of defects in each mask level. As a rule of thumb, defects which are larger than 1/4 of the mininum geometry may potentially cause device malfunction [1]. For devices such as 64 Mbit DRAMs this implies the need of monitoring very low defect densities of defects as small as 0.1 micron. These requirements give rise to new challenges and concepts in defect detection technologies. To meet in-line monitoring requirements, advanced inspection technologies should have: S Ability to cope with pattern densities and topographies which are below the resolution and depth of focus limitations. S Reliable detection of process induced pattern defects as well as micro-contaminations down to 0.1 microns. S High throughput. Present optical inspection technologies include CCD imaging [2], particle detection based on laser scattering techniques [3] and spatial filtering techniques [4], [5], [6]. An extensive survey of automated wafer inspection techniques can be found in [7]. Systems that utilize CCD imaging technique base their detection capability on high and distinct resolution of the pattern. This high resolution is essential for the detection of small differences in the images caused by the presence of defects. Since the smallest possible spot size is in the order of 0.6 micron, when dealing with 0.35 micron technology neither the pattern nor the pattern anomalies are resolved. In addition, defects which are smaller than the optical spot have inherent low contrast. All the above impose severe limitations on the use of CCD technique for micro-defect detection. Laser scattering techniques are used mainly for particle detection on patterned wafers. This technique is limited by its inherent poor resolution, or by pattern variations. For these reasons this technique is used only for moderate (0.5 micron and up) particle detection on layers after deposition as the detection capability is further deteriorated when scanning patterns after etch. Spatial filtering techniques use a blocking spatial filter located in the back-focal plane of the imaging optics in order to suppress the repetitive pattern signals, thus emphasizing the random defects signal. The two main drawbacks of this technique are the need for a specific spatial filter for each wafer type and its disability to inspect random logic devices. The authors believe that the above mentioned wafer inspection techniques have many shortcomings which prevent them from meeting wafer inspection requirements of the mid 90s. This stimulated the need for a new defect detection image acquisition concept. In this paper we describe a new wafer inspection technique which overcomes the limitations of presently available wafer inspection systems. The essence of this new technique is a detection sensor which utilizes a novel concept of Perspective Darkfield Imaging (PDI) combined with pixel-by-pixel die to die comparison. This provides for ultra fast and highly sensitive detection of micro-defects. A built in verification and classification capability enables the differentiation of particles from pattern defects.

Standard patterned wafer for performance evaluation of inspection tools

The defect detection capability of patterned wafer inspection tools is mainly determined by type and size of defects appearing on the wafer. However, detection capability depends not only on defect type and size but also on pattern density and defect location relative to the pattern. In particular, a dense pattern results in higher false alarm probability. Moreover, detection probability decreases with the distance between the defect and the neighboring pattern. The pattern density and defect location are not taken into account in the design of commonly used test wafers. This paper presents the design of a test-wafer aimed at meeting these essential properties. The wafer presented here, exhibiting variable density and spacing characteristics, has a potential of being used as an industry standard for evaluation of patterned wafer inspection tools.