Doron Meshulach

Evidence of printing blank-related defects on EUV masks missed by blank inspection

In this follow-up paper for our contribution at BACUS 2010, first evidence is shown that also the more advanced Lasertec M7360 has missed a few printing reticle defects caused by an imperfection of its EUV mirror, a so-called multilayer defect (ML-defect). This work continued to use a combination of blank inspection (BI), patterned mask inspection (PMI) and wafer inspection (WI) to find as many as possible printing defects on EUV reticles. The application of more advanced wafer inspection, combined with a separate repeater analysis for each of the multiple focus conditions used for exposure on the ASML Alpha Demo Tool (ADT) at IMEC, has allowed to increase the detectability of printing MLdefects. The latter uses the previous finding that ML-defects may have a through-focus printing behavior, i.e., they cause a different grade of CD impact on the pattern in their neighborhood, depending on the focus condition. Subsequent reticle review is used on the corresponding locations with both SEM (Secondary Electron Microscope) and AFM (Atomic Force Microscope). This review methodology has allowed achieving clear evidence of printing ML defects missed by this BI tool, despite of an unacceptable nuisance rate reported before. This is a next step in the investigation if it is possible to avoid actinic blank inspection (ABI) at all, the only presently known technique that is expected to be independent from the presence of a (residual) topography of the ML-defect at the top of the EUV mirror, in detecting those defects. This is considered an important asset of blank inspection, because the printability of a ML-defect on the EUV scanner and its detectability by ABI is determined by the distortion throughout the multilayer, not that at the surface.

Additional evidence of EUV blank defects first seen by wafer printing

First experimental evidence is given that a second generation blank inspection tool has missed a number of printing reticle defects caused by an imperfection of its EUV mirror, i.e., so-called multi-layer defects (ML-defects). This work continued to use a combination of blank inspection (BI), patterned mask inspection (PMI) and wafer inspection (WI) to find as many as possible printing defects on EUV reticles. The application of more advanced wafer inspection, combined with a separate repeater analysis for each of the multiple focus conditions used for exposure on the ASML Alpha Demo Tool (ADT) at IMEC, has allowed to increase the detection capability for printing ML-defects. It exploits the previous finding that ML-defects may have a through-focus printing behavior. They cause a different grade of CD impact on the pattern in their neighborhood, depending on the focus condition. Subsequent reticle review is done on the corresponding locations with both SEM (Secondary Electron Microscope) and AFM (Atomic Force Microscope). This review methodology has allowed achieving clear evidence of printing ML defects missed by this BI tool, despite of a too high nuisance rate, reported before. This establishes a next step in the investigation how essential actinic blank inspection (ABI) is. Presently it is the only known technique whose detection capability is considered independent from the presence of a (residual) distortion of the multi-layer at the top surface. This is considered an important asset for blank inspection, because the printability of a ML-defect in EUV lithography is determined by the distortion throughout the multilayer, not that at the top surface.

Advanced lithography: wafer defect scattering analysis at DUV

Considerable effort is directed towards the development of next-generation lithography processes, addressing the need for transistor densification to meet Moores Law. The aggressive design rule shrinkage requires very tight process windows and induces various types of pattern failure with lithography process variations. Since the lithography process is critical in the wafer fabrication process, the requirements for high sensitivity defect detection in the lithography process becomes tighter as design rules shrink. Analysis of the root cause of the defects and of their interaction with various light sources and optics systems configurations for wafer inspection is essential for understanding the detection limits and requirements from advanced inspection systems targeting future lithography inspection applications. In this work, we present an analysis of wafer defects light scattering and detection for a variety of 3xnm design rule resist structures with various polarizations and optics configurations, at the visible, at UV and at DUV wavelengths. The analysis indicates on the defect scattering and inspection performance trends for a variety of resist structures and defect types, and shows that control of the polarization of the optical inspection system is critical for enhanced scattering and detection sensitivity. The analysis is performed also for the 2xnm and 1xnm design rules showing the advantages of polarized DUV illumination over unpolarized and visible illumination.

AWV: high-throughput cross-array cross-wafer variation mapping

Minute variations in advanced VLSI manufacturing processes are well known to significantly impact device performance and die yield. These variations drive the need for increased measurement sampling with a minimal impact on Fab productivity. Traditional discrete measurements such as CDSEM or OCD, provide, statistical information for process control and monitoring. Typically these measurements require a relatively long time and cover only a fraction of the wafer area. Across array across wafer variation mapping ( AWV) suggests a new approach for high throughput, full wafer process variation monitoring, using a DUV bright-field inspection tool. With this technique we present a full wafer scanning, visualizing the variation trends within a single die and across the wafer. The underlying principle of the AWV inspection method is to measure variations in the reflected light from periodic structures, under optimized illumination and collection conditions. Structural changes in the periodic array induce variations in the reflected light. This information is collected and analyzed in real time. In this paper we present AWV concept, measurements and simulation results. Experiments were performed using a DUV bright-field inspection tool (UVision(TM), Applied Materials) on a memory short loop experiment (SLE), Focus Exposure Matrix (FEM) and normal wafers. AWV and CDSEM results are presented to reflect CD variations within a memory array and across wafers.

Characterization of EUV resists for defectivity at 32nm

Extreme ultraviolet (EUV) lithography is considered as the leading patterning technology beyond the ArF-based optical lithography, addressing the need for transistor densification to meet Moores Law. Theoretically, EUV lithography at 13.5nm wavelength meets the resolution requirements for 1xnm technology nodes. However, there are several major challenges in the development of EUV lithography for mass production of advanced CMOS devices. These include the development of high power EUV light sources, EUV optics, EUV masks, EUV resists, overlay accuracy, and metrology and inspection capabilities. In particular, it is necessary to ensure that effective defect control schemes will be made available to reduce the EUV lithography defectivity to acceptable levels. This paper presents a study on the wafer defectivity and characterization of patterned EUV resists, with the objective of providing a quantitative comparison between the defectivity of different resist materials and different stacks. Patterned wafers were printed using the ASML® EUV full-field Alpha-Demo Tool (ADT 0.25 NA) at imec. The EUV resist patterns were 32nm line/spaces. Several advanced resist types were screened experimentally. The different resist types and stacks were inspected using a DUV laser based brightfield inspection tool, followed by a SEM defect review and CD metrology measurements. The patterns were characterized in terms of defect types and defect density. We identified the major defect types and discuss factors that affect the defectivity level and pattern quality, such as resist type, exposure dose and focus. Defect scattering analysis of DUV polarized light at different polarizations was performed, to indicate on the inspection performance trends for a variety of defect types and sizes of the different resists and stacks. The scattering analysis shows that higher defect scattering is induced using polarized light.

Process variation monitoring (PVM) by wafer inspection tool as a complementary method to CD-SEM for mapping LER and defect density on production wafers

As design rules shrink, Critical Dimension Uniformity (CDU) and Line Edge Roughness (LER) constitute a higher percentage of the line-width and hence the need to control these parameters increases. Sources of CDU and LER variations include: scanner auto-focus accuracy and stability, lithography stack thickness and composition variations, exposure variations, etc. These process variations in advanced VLSI manufacturing processes, specifically in memory devices where CDU and LER affect cell-to-cell parametric variations, are well known to significantly impact device performance and die yield. Traditionally, measurements of LER are performed by CD-SEM or Optical Critical Dimension (OCD) metrology tools. Typically, these measurements require a relatively long time and cover only a small fraction of the wafer area. In this paper we present the results of a collaborative work of the Process Diagnostic & Control Business Unit of Applied Materials® and Nikon Corporation®, on the implementation of a complementary method to the CD-SEM and OCD tools, to monitor post litho develop CDU and LER on production wafers. The method, referred to as Process Variation Monitoring (PVM), is based on measuring variations in the light reflected from periodic structures, under optimized illumination and collection conditions, and is demonstrated using Applied Materials DUV brightfield (BF) wafer inspection tool. It will be shown that full polarization control in illumination and collection paths of the wafer inspection tool is critical to enable to set an optimized Process Variation Monitoring recipe.

Immersion lithography defectivity analysis at DUV inspection wavelength

Significant effort has been directed in recent years towards the realization of immersion lithography at 193nm wavelength. Immersion lithography is likely a key enabling technology for the production of critical layers for 45nm and 32nm design rule (DR) devices. In spite of the significant progress in immersion lithography technology, there remain several key technology issues, with a critical issue of immersion lithography process induced defects. The benefits of the optical resolution and depth of focus, made possible by immersion lithography, are well understood. Yet, these benefits cannot come at the expense of increased defect counts and decreased production yield. Understanding the impact of the immersion lithography process parameters on wafer defects formation and defect counts, together with the ability to monitor, control and minimize the defect counts down to acceptable levels is imperative for successful introduction of immersion lithography for production of advanced DRs. In this report, we present experimental results of immersion lithography defectivity analysis focused on topcoat layer thickness parameters and resist bake temperatures. Wafers were exposed on the 1150i-α-immersion scanner and 1200B Scanner (ASML), defect inspection was performed using a DUV inspection tool (UVisionTM, Applied Materials). Higher sensitivity was demonstrated at DUV through detection of small defects not detected at the visible wavelength, indicating on the potential high sensitivity benefits of DUV inspection for this layer. The analysis indicates that certain types of defects are associated with different immersion process parameters. This type of analysis at DUV wavelengths would enable the optimization of immersion lithography processes, thus enabling the qualification of immersion processes for volume production.