Eiji Itaya

An 800 MHz Low Power Consumption Frequency Synthesizer using Intermittent Operation of a Modified PLL Circuit with Dual Loops

This paper presents a method of reducing the power consumption of the local oscillator for mobile radio communication equipments. The reduction of power consumption is attained by the intermittent stabilization of a PLL circuit in the frequency synthesizer. Whenever the PLL is turned on, there is a transient frequency fluctuation caused by a small amount of frequency and phase difference between the reference signal and the output signal of the programmable divider. Due to this frequency fluctuation, intermittent stabilization has not widely been utilized. We present a new PLL circuit with dual loops to suppress this frequency fluctuation. This new PLL circuit is used for an 800 MHz band frequency synthesizer and can suppress frequency fluctuations within 4 ppm, which is satisfactory for practical use. This frequency synthesizer reduces power consumption by about 35% when the duty ratio is 0.1.