Yoichi Endo

System-on-chip verification process using UML

In this paper, we propose a verification methodology for System-On-Chip (SoC) design using Unified Modeling Language (UML). We introduce UML as a formal model to analyze and formalize the specification. The specification and implementation validation can be performed systematically by introducing UML. We applied our method to a Mobile Media Processors SoC. We improved the quality of ζ the specification written in informal natural language through UML modeling techniques. The test scenarios and coverage metrics for implementation are derived from the UML model systematically. The result shows that our proposal is effective for eliminating errors from both specification and implementation.