Network


Latest external collaboration on country level. Dive into details by clicking on the dots.

Hotspot


Dive into the research topics where Eiko Hayashi is active.

Publication


Featured researches published by Eiko Hayashi.


Applied Physics Express | 2008

GaN-Based Trench Gate Metal Oxide Semiconductor Field-Effect Transistor Fabricated with Novel Wet Etching

Masahito Kodama; Masahiro Sugimoto; Eiko Hayashi; Narumasa Soejima; Osamu Ishiguro; Masakazu Kanechika; Kenji Itoh; Hiroyuki Ueda; Tsutomu Uesugi; Tetsu Kachi

A novel method for fabricating trench structures on GaN was developed. A smooth non-polar (1100) plane was obtained by wet etching using tetramethylammonium hydroxide (TMAH) as the etchant. A U-shape trench with the (1100) plane side walls was formed with dry etching and the TMAH wet etching. A U-shape trench gate metal oxide semiconductor field-effect transistor (MOSFET) was also fabricated using the novel etching technology. This device has the excellent normally-off operation of drain current–gate voltage characteristics with the threshold voltage of 10 V. The drain breakdown voltage of 180 V was obtained. The results indicate that the trench gate structure can be applied to GaN-based transistors.


Japanese Journal of Applied Physics | 2007

A Vertical Insulated Gate AlGaN/GaN Heterojunction Field-Effect Transistor

Masakazu Kanechika; Masahiro Sugimoto; Narumasa Soejima; Hiroyuki Ueda; Osamu Ishiguro; Masahito Kodama; Eiko Hayashi; Kenji Itoh; Tsutomu Uesugi; Tetsu Kachi

We fabricated a vertical insulated gate AlGaN/GaN heterojunction field-effect transistor (HFET), using a free-standing GaN substrate. This HFET has apertures through which the electron current vertically flows. These apertures were formed by dry etching the p-GaN layer below the gate electrodes and regrowing n--GaN layer without mask. The HFET exhibited a specific on-resistance of as low as 2.6 mΩcm2 with a threshold voltage of -16 V. This HFET would be a prototype of a GaN-based high-power switching device.


international symposium on power semiconductor devices and ic s | 1998

New 3-D lateral power MOSFETs with ultra low on-resistance

Tsutomu Uesugi; Masahito Kodama; Sachiko Kawaji; Kenji Nakashima; Yosie Murase; Eiko Hayashi; Yasuichi Mitsushima; Hiroshi Tadano

This paper presents a new 3D lateral power MOSFET which has a double gate and a trench gate/drain structure. The double gate structure decreased its channel resistance, and the trench gate/drain structure decreased its n drift resistance. We realized this structure using solid phase epitaxy and a conventional trench technology. From experimental results, a breakdown voltage of 49.5 V and a specific on-resistance of 42 m/spl Omega//spl middot/mm/sup 2/ were obtained.


international symposium on power semiconductor devices and ic's | 2005

A Study of MIS - AlGaN/GaN HEMTs with SiO/sub 2/ Films as Gate Insulator

M. Sugimoto; Masahito Kodama; Narumasa Soejima; Eiko Hayashi; Tsutomu Uesugi; T. Kachi

Gate insulator formation methods for GaN based MIS-HEMTs were examined. A SiO2 film formed with the HTO deposition method (HTO film) showed excellent properties. The interface state density of the HTO/GaN structure was 2E11 eV -1 cm -2 and the breakdown field was 8.2 MV/cm. MIS-AlGaN/GaN HEMTs were fabricated using the HTO film. A MIS-HEMT with a gate width of 100Pm was characterized by a maximum drain current of 395 mA/mm and a specific on-resistance of 1.7 m:� cm 2 . A high power MIS-HEMT with a gate width of 31.04 mm showed a maximum drain current of more


Archive | 2003

Semiconductor device having current sensing function

Kimimori Hamada; Eiko Hayashi; Masahito Kigami; Yuji Nishibe; Norikazu Ota; Hideshi Takatani; Hideki Toshima; Tsutomu Uesugi; 勉 上杉; 則一 太田; 秀樹 戸嶋; 栄子 林; 雅人 樹神; 公守 濱田; 祐司 西部; 秀史 高谷


Archive | 2006

Group iii nitride semiconductor device having trench or mesa-structure, and manufacturing method thereof

Eiko Hayashi; Masahito Kigami; Masahiro Sugimoto; 雅裕 杉本; 栄子 林; 雅人 樹神


Archive | 2007

Group III nitride based semiconductor device having trench structure or mesa structure and production method therefor

Masahito Kodama; Eiko Hayashi; Masahiro Sugimoto


Archive | 2008

HEMT including MIS structure

Masahito Kodama; Eiko Hayashi; Tsutomu Uesugi; Masahiro Sugimoto


Archive | 2006

Contact hole forming method, and semiconductor device having contact hole

Eiko Hayashi; Toru Kachi; Masahito Kigami; Masahiro Sugimoto; Tsutomu Uesugi; 勉 上杉; 徹 加地; 雅裕 杉本; 栄子 林; 雅人 樹神


Archive | 2004

Structure with upper layer laminated on group iii-v semiconductor layer and its manufacturing method

Eiko Hayashi; Masahito Kigami; Shigemasa Soejima; Masahiro Sugimoto; 成雅 副島; 雅裕 杉本; 栄子 林; 雅人 樹神

Collaboration


Dive into the Eiko Hayashi's collaboration.

Top Co-Authors

Avatar
Top Co-Authors

Avatar

Tsutomu Uesugi

Nagoya Institute of Technology

View shared research outputs
Top Co-Authors

Avatar
Researchain Logo
Decentralizing Knowledge