Masakazu Kanechika

GaN-Based Trench Gate Metal Oxide Semiconductor Field-Effect Transistor Fabricated with Novel Wet Etching

A novel method for fabricating trench structures on GaN was developed. A smooth non-polar (1100) plane was obtained by wet etching using tetramethylammonium hydroxide (TMAH) as the etchant. A U-shape trench with the (1100) plane side walls was formed with dry etching and the TMAH wet etching. A U-shape trench gate metal oxide semiconductor field-effect transistor (MOSFET) was also fabricated using the novel etching technology. This device has the excellent normally-off operation of drain current–gate voltage characteristics with the threshold voltage of 10 V. The drain breakdown voltage of 180 V was obtained. The results indicate that the trench gate structure can be applied to GaN-based transistors.

A Vertical Insulated Gate AlGaN/GaN Heterojunction Field-Effect Transistor

We fabricated a vertical insulated gate AlGaN/GaN heterojunction field-effect transistor (HFET), using a free-standing GaN substrate. This HFET has apertures through which the electron current vertically flows. These apertures were formed by dry etching the p-GaN layer below the gate electrodes and regrowing n--GaN layer without mask. The HFET exhibited a specific on-resistance of as low as 2.6 mΩcm2 with a threshold voltage of -16 V. This HFET would be a prototype of a GaN-based high-power switching device.

Advanced SiC and GaN power electronics for automotive systems

A power switching device is one of the key elements to determine the performance of hybrid electric vehicles (HEVs) and pure electric vehicles (EVs). Recently, the power devices using wide-bandgap semiconductors, such as SiC and GaN, have been intensively developed for the future HEVs and EVs. In this paper, we review a role of the power devices in these automotive systems, the required device characteristics, and the recent status of SiC and GaN power devices.

Control of shape of silicon needles fabricated by highly selective anisotropic dry etching

The process to fabricate a needle-shaped silicon crystal (silicon needle) has been developed. These silicon needles are fabricated by highly selective anisotropic dry etching, where the etching mask is oxygen precipitation in the silicon substrate. In order to apply these silicon needles to field emitters, the shape of the silicon needle should be controlled. This is because a high aspect ratio can lead to electric field enhancement around tips and a flared base of the silicon needle can lead to mechanical and thermal stability. In this article we studied how to control the shape of the silicon needles. We found that the silicon needles with a high aspect ratio could be obtained by either lowering the deposition rate of sidewall passivation film or increasing etching depth, unlike conventional silicon cones fabricated by isotropic dry etching. Furthermore, a high aspect ratio could induce a flared base of the silicon needle, since incident ions were reduced in the vicinity of the base due to a shadowing effect by the silicon needle with a high aspect ratio.The process to fabricate a needle-shaped silicon crystal (silicon needle) has been developed. These silicon needles are fabricated by highly selective anisotropic dry etching, where the etching mask is oxygen precipitation in the silicon substrate. In order to apply these silicon needles to field emitters, the shape of the silicon needle should be controlled. This is because a high aspect ratio can lead to electric field enhancement around tips and a flared base of the silicon needle can lead to mechanical and thermal stability. In this article we studied how to control the shape of the silicon needles. We found that the silicon needles with a high aspect ratio could be obtained by either lowering the deposition rate of sidewall passivation film or increasing etching depth, unlike conventional silicon cones fabricated by isotropic dry etching. Furthermore, a high aspect ratio could induce a flared base of the silicon needle, since incident ions were reduced in the vicinity of the base due to a shadowing e...

A concept of SOI RESURF lateral devices with striped trench electrodes

This paper presents a concept of silicon-on insulator lateral devices based on a reduced surface field (RESURF) principle by striped trench electrodes formed along the current flow direction. These trench electrodes reduce the electric field at the pn junctions sandwiched between the electrodes. We experimentally applied this RESURF technology to a conventional pn/sup -/ lateral diode. As a result, the breakdown voltage was increased from 56 to 104 V without varying the impurity concentration and the length of the n/sup -/ region. This means that the RESURF effect was achieved with the striped trench electrodes. The LDMOS with this RESURF technology was evaluated by simulations. This would be available for 80-V class lateral MOSFETs, used in the forthcoming 42-V automotive systems.

Silicon Needles Fabricated by Highly Selective Anisotropic Dry Etching and Their Field Emission Current Characteristics

A new process to fabricate a silicon needle, whose tip radius is about 5 nm and aspect ratio is about 7, was developed. The silicon needles were fabricated by highly selective anisotropic dry etching. The etching mask was oxygen precipitation, which was formed by nitrogen ion implantation and the subsequent oxidation. The process is simple enough to be integrated with complementary metal-oxide-semiconductor (CMOS) circuits. The density of the silicon needle can be controlled by adjusting the dose for nitrogen ion implantation. The position of the silicon needle can be controlled by adjusting the position for nitrogen ion implantation, because silicon needles are formed only in the nitrogen ion implantation area. Furthermore, using these silicon needles as micro emitters, a field emission diode was fabricated. The Fowler-Nordheim plot shows that the field around the tip of the silicon needles was highly enhanced.

Improvement of Current Collapse by Surface Treatment and Passivation Layer in p-GaN Gate GaN High-Electron-Mobility Transistors

The improvement of current collapses of p-GaN gate GaN high-electron-mobility transistors (HEMTs) caused by the effects of surface treatment and the passivation layer was investigated. The NH3 treatment and high-temperature oxide (HTO) passivation layer on the AlGaN layer are effective in improving the current collapse of a p-GaN gate GaN HEMT. The current collapse at a long time constant (τ= 4 s) could be decreased by the NH3 treatment of the AlGaN layer, because the nitrogen atoms in nitrogen vacancies in the AlGaN layer (trap level: 0.6 eV) would be incorporated, resulting in a low surface density. The current collapse at an intermediate time constant (τ= 11 ms) could also be decreased by the deposition of the HTO passivation layer on the AlGaN layer, because the low-interface-density layer (trap level: 0.4 eV) of HTO/AlGaN would be formed.

Vertical device operation of AlGaN/GaN HEMTs on free-standing n-GaN substrates

We report on the demonstration of normally off and normally on vertical AlGaN/GaN high electron mobility transistors (HEMTs). The normally off device shows the threshold voltage of 1.6 V. The normally on device shows the normalized on resistance of 1.48 mOmega-cm2 and the maximum drain current density of 3.9 kA/cm2. Before then, the dependence of threshold voltage on the thickness of n-GaN in the structure of AlGaN/n-GaN/p-GaN was studied experimentally.

Characterization of plasma etching damage on p-type GaN using Schottky diodes

The plasma etching damage in p-type GaN has been characterized. From current-voltage and capacitance-voltage characteristics of Schottky diodes, it was revealed that inductively coupled plasma (ICP) etching causes an increase in series resistance of the Schottky diodes and compensation of acceptors in p-type GaN. We investigated deep levels near the valence band of p-type GaN using current deep level transient spectroscopy (DLTS), and no deep level originating from the ICP etching damage was observed. On the other hand, by capacitance DLTS measurements for n-type GaN, we observed an increase in concentration of a donor-type defect with an activation energy of 0.25eV after the ICP etching. The origin of this defect would be due to nitrogen vacancies. We also observed this defect by photocapacitance measurements for ICP-etched p-type GaN. For both n- and p-type GaN, we found that the low bias power ICP etching is effective to reduce the concentration of this defect introduced by the high bias power ICP etching.

n-type AlN layer by Si ion implantation

n-type AlN layer was obtained by Si ion implantation and the subsequent activation annealing. Si ions were implanted to an unintentionally doped AlN layer grown on a sapphire substrate at an acceleration energy of 90keV with a dose of 5×1015cm−2. The activation annealing was performed at 1400°C for 10min in a nitrogen ambient. We characterized it by Hall-effect measurements in a temperature range from 373to873K. These revealed that the carrier type exhibited n type, the carrier concentration at 373K was approximately 8.8×1015cm−3, and that the Hall mobility at 373K was as high as 20cm2V−1s−1. The donor ionization energy was 294meV. The Hall mobility varied as T−1.1 (T is the absolute temperature) above 523K.