Eing-Seob Cho

Advanced PRML data detector for high density recording

An advanced PRML data recovery system is presented for a high-density recording. The system consists of three major hardware units, which are DC offset compensator, adaptive equalizer, and Viterbi detector with level adaptation scheme. The experiment based on an improved PRML scheme and FPGA hardware realization shows highly reliable performance of data detection up to 35GB recording density. The SER experiment result for 35GB shows that the detector using the proposed PRML yields a result to meet the SER limit of 4.0x10-3 with a margin of 0.45° for tangential and 0.55° for radial tilt. And the base SER marks 7.0x10-5 when there is no tangential and radial tilt error.

High-Performance Mixed PRML Architecture for Optical Data Storage System

A new mixed analog/digital partial response maximum likelihood (PRML) architecture for the optical drive system is presented. To realize a high-speed, low-power and low-cost solution, new data and clock recovery circuits are proposed. The proposed architecture is based on the efficient combination of digital and analog circuits for providing high-speed and low-power data detection for optical data storage systems. The presented circuit shows increased operating speed by 67%, reduced power consumption by 28% and reduced area by 42%, therefore it provides a high-speed, low-power and low-cost system on chip solution for the future optical drive system. A test chip produced is fabricated using 0.18 µm CMOS technology and the product has been proved to demonstrate the performance of the proposed architecture.

Signal quality measurement using channel identification method for high-density optical channel

A new signal quality measurement method for high-density optical read/write system is presented. In this method, the signal quality is expressed in detail as a figure of the coefficients in accordance with channel characteristics.

High speed mixed analog/digital PRML architecture for optical data storage system

New mixed analog/digital PRML (partial response maximum likelihood) architecture for the optical drive system is presented. In order to realize high speed, low power and low cost solution, new data and clock recovery circuits are proposed. The proposed architecture is based on the efficient combination of digital and analog circuits to provide high speed and low power data detection for optical data storage system. The presented circuit shows increased operating speed by 67%, reduced power consumption by 28% and area by 42%, therefore it provides high speed, low power and low cost SOC solution for the future optical drive system. A test chip produced is fabricated using 0.18 /spl mu/m CMOS technology and the product has been proved to demonstrate the performance of the proposed architecture.

Fast and accurate frequency detection algorithm for robust timing recovery

A new digital frequency detection algorithm is presented for the fast and accurate frequency detection in optical disc systems. The proposed algorithm is based on the histogram analysis of input data sequences. By using the proposed algorithm, the detection delay is reduced to 1/4 of the conventional delay with the reliable accuracy and the detection resolution is improved by 230 times at the conventional detection delay. Performance improvements can guarantee the robust timing recovery in optical disc systems.