Hyun-Su Chae

A fast frequency/mode switching quadrature SSB mixer/amplifier for the low power MTG in MB-OFDM UWB radio transceiver

A fast frequency/mode switching SSB mixer/amplifier topology is proposed for the implementation of low power multi-tone generator (MTG) in MB-OFDM UWB system. The proposed SSB mixer/amplifier topology is fabricated for the generation of mode-1 band center carrier with 0.18mum CMOS technology. The measurement result shows the 8.5ns mixer/amplifier mode switching time. The center carrier output power levels are -13.0dBm, -12.88dBm, and -14.33dBm in 3432MHz, 3960MHz, and 4488MHz, respectively. The harmonic suppressions are -40dBc and -30dBc in 3432MHz and 4488MHz, where the SSB mixer mode is selected. In the amplifier mode, the 3960MHz tone does not have any harmonics tone. For measurement, 1.8V supply voltage is used while drawing 26mA total current

High-Performance Mixed PRML Architecture for Optical Data Storage System

A new mixed analog/digital partial response maximum likelihood (PRML) architecture for the optical drive system is presented. To realize a high-speed, low-power and low-cost solution, new data and clock recovery circuits are proposed. The proposed architecture is based on the efficient combination of digital and analog circuits for providing high-speed and low-power data detection for optical data storage systems. The presented circuit shows increased operating speed by 67%, reduced power consumption by 28% and reduced area by 42%, therefore it provides a high-speed, low-power and low-cost system on chip solution for the future optical drive system. A test chip produced is fabricated using 0.18 µm CMOS technology and the product has been proved to demonstrate the performance of the proposed architecture.

A Fast Hopping Frequency Synthesizer for UWB Systems in a CMOS Technology

A 3 to 5 GHz fast hopping frequency synthesizer for multi-band OFDM UWB applications is designed using a 0.18 mum CMOS technology. The frequency synthesizer operates in the mode 1 bands (centered at 3432 MHz, 3960 MHz, and 4488 MHz). Single-sideband mixer up-converts or down-converts the 528 MHz quadrature signals of ring VCO mixing 3960 MHz LC VCO signals. The sideband suppression is less than -32 dBc for 3432 MHz and -26 dBc for 4488 MHz and band switching time from 4488 MHz to 3432 MHz is measured about 2 ns. Phase noise of the LC VCO and the ring VCO is about -110 dBc/Hz and -98 dBc/Hz at 1 MHz offset frequency, respectively. The total power consumption of the proposed frequency synthesizer is about 68 mW with a 1.8 V supply voltage

Analog Baseband Chain in a 0.18 μm Standard Digital CMOS Technology for IEEE802.15.3a (UWB) Receiver

Today UWB (ultra-wideband) communication is gaining a great attention from consumer electronic-industry and is expected to be adopted for many WPAN (wireless personal area network) applications. UWB (Ultra- wideband) communication standard is based the form of direct sequence or OFDM (orthogonal frequency division multiplexing) for high-date-rate application like IEEE 802.15.3a [1]. This paper demonstrates a successful implementation and experimental verification of a CMOS analog baseband chain - variable gain amplifier and low pass filter - for a UWB wireless PAN (personal area network) receiver in a 0.18 μm CMOS process. The experiments features 40 dB linear scaled output gain and a total current of 30 mA.

High speed mixed analog/digital PRML architecture for optical data storage system

New mixed analog/digital PRML (partial response maximum likelihood) architecture for the optical drive system is presented. In order to realize high speed, low power and low cost solution, new data and clock recovery circuits are proposed. The proposed architecture is based on the efficient combination of digital and analog circuits to provide high speed and low power data detection for optical data storage system. The presented circuit shows increased operating speed by 67%, reduced power consumption by 28% and area by 42%, therefore it provides high speed, low power and low cost SOC solution for the future optical drive system. A test chip produced is fabricated using 0.18 /spl mu/m CMOS technology and the product has been proved to demonstrate the performance of the proposed architecture.

An improved architecture of the mixed mode clock/data recovery for DVD read channel

A mixed mode clock and data recovery module for DVD player and recorder is developed. The proposed system is the improved version of the conventional one which integrates an analog front end, a clock recovery circuit, and a partial response maximum likelihood (PRML) employing PR (1,2,2,1) channel model. For achieving a low-power, low-cost and high speed read-channel IC, the digital adaptive equalizer in the conventional DVD system is replaced with a waveform controller. Also, an analog charge-pump and external low pass filter (LPF) are employed instead of the digital LPF in the clock recovery loop for higher speed. The proposed architecture reduces power consumption and die size by 28.3% and 41.8%, respectively. Gain with the PRML technique is about 4 dB superior to that of a slicer at BER 10/sup -4/. The chip has been fabricated with 0.18 /spl mu/m one-poly five-metal CMOS technology.