Eisuke Saneyoshi
NEC
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Publication
Featured researches published by Eisuke Saneyoshi.
international solid-state circuits conference | 2010
Eisuke Saneyoshi; Koichi Nose; Masayuki Mizuno
Scaling has accelerated transistor degradation with respect to aging, especially for Negative Bias Temperature Instability (NBTI), which can cause more than a 10% degradation in delay [1]. It is known that in NBTI conditions, delay degradation decreases quickly after the DC-stress has been removed. Conventional aging monitors [3][4] have difficulty in characterizing NBTI accurately because they require long-term observations (more than 1µs) of delay degradation, whilst recovery from delay degradation will be accomplished in less than 1µs [2].
symposium on vlsi circuits | 2008
Eisuke Saneyoshi; Koichi Nose; Mikihiro Kajita; Masayuki Mizuno
Presented here is a thermal sensor, based on transistor off-leakage current, that allows measurement error of less than 3.1degC at 90degC and less than 2degC at 10% Vdd deviation. For experimental evaluation, 11 thermal sensors, each of which occupied only 35 mum times 35 mum area, were placed on a chip, and both the location of a hotspot and the overall temperature distribution were successfully measured and agreed with simulation.
Archive | 2010
Eisuke Saneyoshi; Koichi Nose; Masayuki Mizuno
Archive | 2011
Eisuke Saneyoshi; Koichi Nose
Archive | 2014
Koji Kudo; Hisato Sakuma; Hitoshi Yano; Kazuhiko Aoki; Yoshiho Yanagita; Yuma Iwasaki; Ryo Hashimoto; Eisuke Saneyoshi; Takahiro Toizumi
Archive | 2011
Eisuke Saneyoshi; 永典 實吉; Koichi Nose; 浩一 野瀬
Archive | 2014
Koji Kudo; Hisato Sakuma; Hitoshi Yano; Kazuhiko Aoki; Yoshiho Yanagita; Yuma Iwasaki; Ryo Hashimoto; Eisuke Saneyoshi; Takahiro Toizumi
Archive | 2012
Eisuke Saneyoshi
Archive | 2008
Eisuke Saneyoshi; Koichi Nose; Mikihiro Kajita; Masayuki Mizuno
Archive | 2017
Eisuke Saneyoshi; Koji Kudo; Ryo Hashimoto; Kosuke Homma; Takahiro Toizumi