Koichi Nose

A super cut-off CMOS (SCCMOS) scheme for 0.5-V supply voltage with picoampere stand-by current

A super cut-off CMOS (SCCMOS) scheme is proposed and demonstrated by measurement to achieve high-speed and low stand-by current CMOS VLSIs in sub-1-V supply voltage regime. By overdriving the gate of a cut-off MOSFET, the SCCMOS suppresses leakage current below 1 pA per logic gate in a stand-by mode while high-speed operation in an active mode is possible with low-threshold voltage of 0.1-0.2 V. The SCCMOS pushes the low-voltage operation limit 0.2 V further down compared with conventional schemes while maintaining the same stand-by current level.

Optimization of VDD and VTH for low-power and high speed applications

Closed-form formulas are presented for optimum supply voltage (V/sub DD/) and threshold voltage (V/sub TH/) that minimize power dissipation when technology parameters and required speed are given. The formulas take into account short-channel effects and the variation of V/sub TH/ and temperature. Using typical device parameters, it is shown that a simple guideline to optimize the power consumption is to set the ratio of maximum leakage power to total power about 30%. Extending the analysis, the future VLSI design trend is discussed. The optimum V/sub DD/ coincides with the SIA roadmap and the optimum V/sub TH/ for logic blocks at the highest temperature and at the lowest process variation corner is in the range of 0 V-0.1 V over generations.

Analysis and future trend of short-circuit power

A closed-form expression for short-circuit power dissipation of CMOS gates is presented which takes short-channel effects into consideration. The calculation results show good agreement with the SPICE simulation results over wide range of load capacitance and channel length. The change in the short-circuit power, P/sub S/, caused by the scaling in relation to the charging and discharging power, P/sub D/, is discussed and it is shown that basically power ratio, P/sub S//(P/sub D/+P/sub S/), will not change with scaling if V/sub TH//V/sub DD/ is kept constant. This paper also handles the short-circuit power of series-connected MOSFET structures which appear in NAND and other complex gates.

V/sub TH/-hopping scheme to reduce subthreshold leakage for low-power processors

In order to suppress the power consumption in low-voltage processors, a threshold voltage hopping (V/sub TH/-hopping) scheme is proposed where the threshold voltage is dynamically controlled through software depending on a workload. V/sub TH/-hopping is shown to reduce the power to 18 % of the fixed low-threshold voltage circuits in 0.5-V supply voltage regime for multimedia applications. A positive back-gate bias scheme with V/sub TH/-hopping is presented for the high-performance and low-voltage processors. In order to verify the effectiveness of V/sub TH/-hopping, a small-scale RISC processor with V/sub TH/-hopping capability and the positive back-gate bias scheme is fabricated in a 0.6-/spl mu/m CMOS technology. MPEG4 encoding is simulated based on the measured data. The result shows that 86% power saving can be achieved by using V/sub TH/-hopping compared with the fixed positive back-gate bias scheme.

A 1ps-Resolution Jitter-Measurement Macro Using Interpolated Jitter Oversampling

An in-field real-time successive jitter-measurement macro is developed. It features interpolated jitter oversampling and feedforward calibration that help attain 1ps resolution and a hierarchical Vernier jitter-measurement technique that exploits the trade-off between rms and deterministic jitter measurement characteristics

V/sub TH/-hopping scheme for 82% power saving in low-voltage processors

A threshold voltage hopping (V/sub TH/-hopping) scheme is proposed where V/sub TH/ is dynamically controlled through software depending on a workload. V/sub TH/-hopping is shown to reduce the power to 18% of the fixed low-V/sub TH/ circuits in 0.5 V supply voltage regime for multimedia applications. A positive back-gate bias scheme within V/sub TH/-hopping is presented for the high-performance and low-voltage processors. The measurement result shows about 90% leakage power reduction is possible by using V/sub TH/-hopping.

Two schemes to reduce interconnect delay in bi-directional and uni-directional buses

As the device dimension is scaled down, interconnect RC delay becomes dominant performance limiter in high-performance VLSIs. Another issue in the submicron interconnects is a drastic increase of coupling capacitance due to the higher aspect ratio to reduce the interconnect resistance. The increase of the coupling capacitance degrades signal integrity, inducing noise problems and delay fluctuation problems. Buffer insertion (repeater insertion) is one of the most effective ways to decrease the interconnect delay. The original buffer insertion, however, cannot be applied to bi-directional buses because the buffer is uni-directional in nature. Some circuit configurations that can be applied to bi-directional buses have been proposed. These circuits turn out to be prone to malfunctions when there is a noise from adjacent lines in scaled down interconnect systems where capacitive coupling is large. A new buffer insertion scheme for bi-directional buses, namely the dual-rail bus (DRB) scheme, which does not have noise problems is proposed and measured in this paper. Another proposal is on a high-speed buffer insertion scheme for uni-directional buses by making use of staggered firing. The staggered firing bus (SFIB) is proposed and measured.

A 27% Active-Power-Reduced 40-nm CMOS Multimedia SoC With Adaptive Voltage Scaling Using Distributed Universal Delay Lines

AVS technique for extremely scaled SoCs has been developed. To reduce design cost, we have developed a supply voltage control scheme employing universal delay line (UDL), rather than a replica delay line, for monitoring the critical path delay (TCRIT). The UDL can be used in any product without any need for customizing. In addition, averaging the results of distributed 4 monitors with a pitch of 3 mm in a chip can reduce errors due to within-die variation by half. With these techniques, proposed scheme produces equivalent or less error to TCRIT than does a conventional scheme that uses a single critical path replica as a delay monitor, even with simple monitor design. We have shown that 40-nm CMOS SoCs using our AVS can reduce active power by 27%.

A precise-tracking NBTI-degradation monitor independent of NBTI recovery effect

Scaling has accelerated transistor degradation with respect to aging, especially for Negative Bias Temperature Instability (NBTI), which can cause more than a 10% degradation in delay [1]. It is known that in NBTI conditions, delay degradation decreases quickly after the DC-stress has been removed. Conventional aging monitors [3][4] have difficulty in characterizing NBTI accurately because they require long-term observations (more than 1µs) of delay degradation, whilst recovery from delay degradation will be accomplished in less than 1µs [2].

Design methodology and optimization strategy for dual-V/sub TH/ scheme using commercially available tools

Design methodology for dual-V/sub TH/ scheme using commercially available tools is presented and optimization strategy for the dual-V/sub TH/ scheme is discussed. In order to suppress the power consumption, it is shown that using library cells that have various combinations of V/sub TH/s is not needed. The cell library, which contains logic gates with all high V/sub TH/ transistors and all low VTH transistors, is sufficient to reduce leakage power. 0.1 V is shown to be the optimum value for V/sub TH/ difference between V/sub TH,HIGH/ and V/sub TH,LOW/ in terms of power reduction.