Eitan Shauly

Activation improvement of ion implanted boron in silicon through fluorine co-implantation

In this study, boron diffusion and activation characteristics of samples implanted with F co-implantation were studied to meet the challenge of lower sheet resistance. Samples were implanted with F co-implantation in a dose range of 0 (no F) to 5×1015 cm−2, at a fixed energy of 25 keV, followed by 950 °C/10 s rapid thermal annealing. It was found that although the fluorine has a negligible affect on the boron diffusion at the specified conditions, a higher F dose reduced the boron sheet resistance. Using reverse modeling, the boron solid solubility at 950 °C was extracted as function of the F co-implant concentration. For low fluorine doses (0–1×1014 cm−2), the boron solid solubility is similar to that reported in the literature (9×1019 cm−3). At higher doses, boron solid solubility increased by 25% and even 50% for F co-implantation doses of 1×1015 and 5×1015, respectively. We suggest that the F co-implantation terminates some of the defects created by the implantation, inactivating the defects and impro...

MBPCA application for fault detection in NMOS fabrication

This paper describes the application of model-based principal component analysis (MBPCA) to the identification and isolation of faults in NMOS manufacture. In MBPCA, multivariate statistics are applied to the analysis of the portion of the data variance that is unexplained by models based on material and energy balances carried out on the unit operations used in manufacture. It is demonstrated that the failure detection and isolation performance achievable using the model-based procedure exceeds that of commonly used univariate SPC or conventional PCA approaches.

Full flow for transistor simulation based on edge-contour extraction and advanced SPICE simulation

A methodology for predicting on and off-state transistor performance is described in this paper. In general, this flow consists of systematic Edge-Contour-Extraction (ECE) from devices under the manufacturing, followed by device simulation. Gate parameter extraction calculates an equivalent gate length and width (Leq, Weq) for non-rectangular gates. The methodology requires a model describing MOSFET behavior of current versus width for various gate lengths and voltages. Non-rectangular gates are described by a weighted sum of the currents from a discrete representation (i.e. Total gate current is determined by a weighted sum since the current distribution is not homogeneous along the channel). Thus, for a given L, W and V, the current should be discoverable from the calibrated model. This approach is more general than previous work as both Leq and Weq are determined for a given voltage which permits the model to predict on and off-current with a single spice netlist as opposed to previous work which only considered adjustments to the channel length. In this work, two transistor series at two different drawn pitch conditions (dense and isolated) were manufactured, followed by state-of-the-art ECE. The contours obtained directly by SEM measurements were used to perform an electrical device simulation for each individual transistor in the series. This paper demonstrates the possibility to analyze the transistors electrical performance at nominal and off-process conditions. The presented simulation flow provides the advantage of early-in-time prediction of the transistor performances, measuring large volume of devices in a fast and accurate fashion.

Improvement of Temperature Coefficient of Resistance by Co-Implantation of Argon or Xenon or Fluorine in Boron Implanted Polysilicon Resistors

This paper proposes a new method to decrease the absolute value of temperature coefficient of resistance (TCR) in P-type boron implanted polysilicon resistors, at a given intermediate sheet resistance values, by selecting an optimized combination of boron doping implant conditions with co-implantation conditions. The co-implantation ion species that were investigated are fluorine, argon and xenon. Each of the co-implantation species was studied at three different co-implantation conditions and two different boron doping implant conditions of dose and energy. The stopping and range of ions in matter (SRIM) Monte Carlo simulation and thermawave measurements were used in order to set the experimental conditions and to evaluate the crystal damage and the amorphous layer depth created by the co-implantation. Amorphous layer is defined in this work as highly disordered material with vacancies concentration above 10% of the crystal density. Electrical measurements show that co-implantation causes a remarkable change in sheet resistance and TCR. Deeper co-implanted amorphous layer increases TCR and decreases sheet resistance. Typical polysilicon TCR is negative, while the TCR of a single crystal is positive. An improvement of TCR is defined at this work as minimum TCR in absolute values, which is lower sensitivity of sheet resistance to operational temperatures. Co-implantation that created deep amorphous layer in the polysilicon, decreases the TCR absolute values by up to ~75 % at the lower boron doping implant samples. Deep co-implanted amorphous layer also decreases sheet resistance by up to ~40% in both of the boron doping implants. Co-implanted xenon and fluorine exhibit similar effect on sheet resistance and TCR, while the co-implanted argon effect is weaker in comparison to samples without co-implantation. The increase of TCR and the decrease of sheet resistance are attributed to grains regrowth during the rapid thermal anneal (RTP). The regrowth of the co-implanted amorphous layer creates larger grains with less grain boundaries and less defects in comparison to the polysilicon samples without co-implantation. Analysis by X-ray diffractometer (XRD) and atomic force microscope (AFM) supports the suggested model.

Transistor layout configuration effect on actual gate LER

The importance of Line Edge Roughness (LER) and Line Width Roughness (LWR) has long surpassed its effect on process control. As devices scale down, the roughness effects have become a major hindrance for further advancement along Moores law. Many studies have been conducted over the years on the sensitivity of LER to various changes in the materials and the process, which have been considered the main way to tackle the problem - especially through Photoresist improvement. However, despite the increased development of DFM tools in recent years, limited research was done as to LER sensitivity to layout, and the research that was done was limited to proximity effects. In this paper, we study the sensitivity of LER to the layout around the transistor, defined by the gate structure of poly over AA (Active Area). Using different types and geometries of transistors, we found that the poly-gate LER is sensitive to the structure of the Active Area around it (source/drain from gate to contact, both shape and length). Using local LER measurement (moving standard deviation of poly edge location), we found a clear correlation between LER value and the length of the AA/STI boundary located at a close range. Longer AA edges yield higher LER, as proved by comparing gate LER of dog-bone transistor with classical transistor. Based on these results, we suggest that LER is sensitive not only to proximity effects, but also to the layout of underlying layers, through the effect of light scattering of the edges during the lithographic process.

Experimental extraction of point defects parameters needed for 2-D process modeling using reverse modeling

This work deals with the simulation of two-dimensional impurity diffusion in CMOS silicon devices. The reverse modeling method was used to determine the diffusion coefficient (D/sub I/), surface recombination rate of defects (K/sub I/) and the characteristics of the injecting source. Analysis showed similarity between D/sub I/ in the 2D system compared with the value obtained from non-patterned samples. The results for D/sub I/ and K/sub I/ are very well described by the Arrhenius expressions. D/sub I/ was found to be related to the substrate type e.g. EPI or CZ. The values of K/sub I/ related to the interface type, oxidizing or nonoxidizing (SiO/sub 2/ or Si/sub 3/N/sub 4/).

LER characterization and impact on 0.13-μm lithography for OPC modeling

This paper presents Line Edge Roughness (LER) characterization for Tower Semiconductor 0.13um Standard Logic technology with advanced OPC modeling. First the applicability of top-view CD-SEM and AFM for LER measurement of poly-Si transistor gate characterization is studied. Then the influence of aerial image contrast and the gradient of the photoactive component on LER is reviewed and the possibility of minimizing LER by optimizing process conditions is considered. Finally the impact of LER on OPC model accuracy is reviewed. Model predictability with and without LER taken into account is compared.

Yield enhancement by modification of wet oxide strip processes

The purpose of this work was to reduce isolation oxide defect density and improve gate oxide integrity by modification of wet oxide strip and pre-diffusion clean. Work was done on 1.0 micrometers and 0.8 micrometers M2CMOS twin-well technology. Twin-wells are defined by local oxidation process using nitride layer. Active area is also defined by local oxidation. MOS gate is built of POCl3 doped polysilicon on top of 185A oxide.