Peter Nikolsky

Application challenges with double patterning technology (DPT) beyond 45 nm

Double patterning technology (DPT) is a promising technique that bridges the anticipated technology gap from the use of 193nm immersion to EUV for the half-pitch device node beyond 45nm. The intended mask pattern is formed by two independent patterning steps. Using DPT, there is no optical imaging correlation between the two separate patterning steps except for the impact from mask overlay. In each of the single exposure step, we can relax the dense design pattern pitches by decomposing them into two half-dense ones. This allows a higher k1 imaging factor for each patterning step. With combined patterns, we can achieve overall k1 factor that exceeds the conventional Rayleigh resolution limit. This paper addresses DPT application challenges with respect to both mask error factor (MEF) and 2D patterning. In our simulations using DPT with relaxed feature pitch for each exposure step, the MEF for the line/space is fairly manageable for 32nm half-pitch and below. The real challenge for the 32nm half-pitch and below with DPT is how to deal with the printing of small 2D features resulting from the many cutting sites due to feature decomposition. Each split of a dense pattern generates two difficult-to-print line-end type features with dimension less than one-fifth or one-sixth of ArF wavelength. Worse, the proximity environment of the 2D cut features can then become quite complex. How to stitch them correctly back to the original target requires careful attention. Applying target bias can improve the printing performance in general. But using a model-based stitching error correction method seems to be a preferred solution.

Development of layout split algorithms and printability evaluation for double patterning technology

When using the most advanced water-based immersion scanner at the 32nm node half-pitch, the image resolution will be below the k1 limit of 0.25. If EUV technology is not ready for mass production, double patterning technology (DPT) is one of the solutions to bridge the gap between wet ArF and EUV platforms. DPT technology implies a patterning process with two photolithography/etching steps. As a result, the critical pitch is reduced by a factor of 2, which means the k1 value could increase by a factor of 2. Due to the superimposition of patterns printed by two separate patterning steps, the overlay capability, in addition to image capability, contributes to critical dimension uniformity (CDU). The wafer throughput as well as cost is a concern because of the increased number of process steps. Therefore, the performance of imaging, overlay, and throughput of a scanner must be improved in order to implement DPT cost effectively. In addition, DPT requires an innovative software to evenly split the patterns into two layers for the full chip. Although current electronic design automation (EDA) tools can split the pattern through abundant geometry-manipulation functions, these functions, however, are insufficient. A rigorous pattern split requires more DPT-specific functions such as tagging/grouping critical features with two colors (and hence two layers), controlling the coloring sequence, correcting the printing error on stitching boundaries, dealing with color conflicts, increasing the coloring accuracy, considering full-chip possibility, etc. Therefore, in this paper we cover these issues by demonstrating a newly developed DPT pattern-split algorithm using a rule-based method. This method has one strong advantage of achieving very fast processing speed, so a full-chip DPT pattern split is practical. After the pattern split, all of the color conflicts are highlighted. Some of the color conflicts can be resolved by aggressive model-based methods, while the un-resolvable conflicts, known as native conflicts, require a change in the design to achieve a DPTfriendly design. A model-based stitching boundary correction is then used after the color conflicts are corrected. Finally the OPC treatment is implemented on both split layouts. The OPC challenges are highlighted by examining the printed image from both exposures. The key concepts described above with additional full chip requirements have been successfully implemented onto Brions TachyoTM system. The efficiency and accuracy of the DPT pattern split method were evaluated on a full-chip layout. The results show that the algorithm proposed in this paper is a viable solution for the DPT pattern split.

Pattern split rules! A feasibility study of rule based pitch decomposition for double patterning

To fulfill Moores law the R&D stage of 3x nm HP nodes will have to be reached in 2008. Conventional DUV immersion technology is resolution limited to half pitch values exceeding 40 nm. Double Patterning Technology (DPT) is a major candidate to reach the 3x nm node in time. Geometrical pattern split, doubling the pitch, is one of the major steps of DPT. We present a feasibility study of the Rule Based (RB) DPT approach to pattern splitting based on a representative and reviewed selection of clips and full-mask designs.

Litho and patterning challenges for memory and logic applications at the 22-nm node

In this paper we look into the litho and patterning challenges at the 22nm node. These challenges are different for memory and logic applications driven by the difference in device layout. In the case of memory, very small pitches and CDs have to be printed, close to the optical diffraction limit (k1) and resist resolution capability. For random logic applications e.g. the printing of SRAM, real pitch splitting techniques have to be applied for the first time at the 22nm node due to the aggressive dimensions of extreme small and compact area and pitch of SRAM bitcell. Common challenges are found for periphery of memory and random logic SRAM cells: here the Best Focus difference per feature type, limits the Usable Depth of Focus.

Feasibility study of the approach to Flare, Shadowing, Optical and Process corrections for EUVL OPC

The switch from 193i to EUV Photolithography will bring some fundamental changes in exposure. The flare levels of an EUV machine are significantly higher compared with standard 193i machines. Moreover shadow effects on the reticle are not equivalent to 193i. It is inevitable that these fundamentals require modifications in the Optical Proximity Correction (OPC) flow. In this paper in collaboration with ASML BRION the critical enabling steps of the Mask Data Preparation (MDP) for EUVL, Flare, Shadowing and Optical and Process Corrections (OPC), are investigated. We measured the needs of the EUV MDP flow against the capabilities of a state-of-the art OPC flow built for 193i. Adaptations are being made to implement features which are currently not available in a 193i based flow. We present a feasibility study of the Model Based approach to the EUV OPC on a wide selection of features. Also we demonstrate simulations and verification of the EUV modeling capabilities of the TachyonTM with various levels and ranges of flare and prove the applicability of the reviewed approach to the process development for the 27nm EUV node.. We also evaluated the accuracy of the EUV OPC modeling and expected OPC corrections on the reviewed selection of clips as a substantial part of the overall CDU budget. Finally an overall EUV OPC flow as a manufacturable solution based on the Tachyons predictions and ASMLs knowledge of Photolithography was discussed.

Improved model predictability by machine data in computational lithography and application to laser bandwidth tuning

Computational lithography (CL) is becoming more and more of a fundamental enabler of advanced semiconductor processing technology, and new requirements for CL models are arising from new applications such as model-based process tuning. In this paper we study the impact of realistic machine parameters that can be incorporated in a modern CL model, and provide an experimental assessment of model improvements with respect to prediction of scanner tuning effects. The data demonstrates improved model accuracy and prediction by inclusion of scanner-type specific modeling capabilities and machine data in the CL model building process. In addition to scanner effects, we study laser bandwidth tuning effects and the accuracy of corresponding model predictions by comparison against experimental data. The data demonstrate that the models predict well wafer CD variations resulting from laser BW tuning. We also find that using realistic spectral density distribution of the laser can provide more accurate results than the commonly assumed modified Lorentzian line shape.

Mask characterization for critical dimension uniformity budget breakdown in advanced extreme ultraviolet lithography

Abstract. As the International Technology Roadmap for Semiconductors critical dimension uniformity (CDU) specification shrinks, semiconductor companies need to maintain a high yield of good wafers per day and high performance (and hence market value) of finished products. This cannot be achieved without continuous analysis and improvement of on-product CDU as one of the main drivers for process control and optimization with better understanding of main contributors from the litho cluster: mask, process, metrology and scanner. We will demonstrate a study of mask CDU characterization and its impact on CDU Budget Breakdown (CDU BB) performed for advanced extreme ultraviolet (EUV) lithography with 1D (dense lines) and 2D (dense contacts) feature cases. We will show that this CDU contributor is one of the main differentiators between well-known ArFi and new EUV CDU budgeting principles. We found that reticle contribution to intrafield CDU should be characterized in a specific way: mask absorber thickness fingerprints play a role comparable with reticle CDU in the total reticle part of the CDU budget. Wafer CD fingerprints, introduced by this contributor, may or may not compensate variations of mask CDs and hence influence on total mask impact on intrafield CDU at the wafer level. This will be shown on 1D and 2D feature examples. Mask stack reflectivity variations should also be taken into account: these fingerprints have visible impact on intrafield CDs at the wafer level and should be considered as another contributor to the reticle part of EUV CDU budget. We also observed mask error enhancement factor (MEEF) through field fingerprints in the studied EUV cases. Variations of MEEF may play a role towards the total intrafield CDU and may need to be taken into account for EUV lithography. We characterized MEEF-through-field for the reviewed features, with results herein, but further analysis of this phenomenon is required. This comprehensive approach to quantifying the mask part of the overall EUV CDU contribution helps deliver an accurate and integral CDU BB per product/process and litho tool. The better understanding of the entire CDU budget for advanced EUVL nodes achieved by Samsung and ASML helps extend the limits of Moore’s Law and to deliver successful implementation of smaller, faster and smarter chips in semiconductor industry.

CD uniformity optimization at volume ramp up stage for new product introduction

In this paper we describe the joint development and optimization of the critical dimension uniformity (CDU) at an advanced 300 mm ArFi semiconductor facility of SK Hynix in the high volume device. As the ITRS CDU specification shrinks, semiconductor companies still need to maintain high wafer yield and high performance (hence market value) even during the introduction phase of a new product. This cannot be achieved without continuous improvement of the on-product CDU as one of the main drivers for yield improvement. ASML Imaging Optimizer is one of the most efficient tools to reach this goal. This paper presents experimental results of post-etch CDU improvement by ASML imaging optimizer for immature photolithography and etch processes on critical features of 20nm node. We will show that CDU improvement potential and measured CDU strongly depend on CD fingerprint stability through wafers, lots and time. However, significant CDU optimization can still be achieved, even for variable CD fingerprints. In this paper we will review point-to-point correlation of CD fingerprints as one of the main indicators for CDU improvement potential. We will demonstrate the value of this indicator by comparing CD correlation between wafers used for Imaging Optimizer dose recipe development, predicted and measured CDU for wafers and lots exposed with various delays ranging from a few days to a month. This approach to CDU optimization helps to achieve higher yield earlier in the new product introduction cycle, enables faster technology ramps and thereby improves product time to market.

Scanner-to-scanner CD analysis and control in an HVM environment

Shrinking pattern sizes dictate that scanner-to-scanner variations for HVM products shrink proportionally. This paper shows the ability to identify (a subset of) root causes for mismatch between ArF immersion scanners using scanner metrology. The root cause identification was done in a Samsung HVM factory using a methodology (Proximity Matching Budget Breakdown or PromaBB) developed by ASML. The proper identification of root causes-1 helps to select what combination of scanner control parameters should be used to reduce proximity differences of critical patterns while minimizing undesirable side effects from cross-compensation. Using PromaBB, the difference between predicted and measured CD mismatch was below 0.2nm. PromaBB has been proposed for HVM implementation at Samsung in combination with other ASML fab applications: Pattern Matcher Full Chip (PMFC), Image Tuner and FlexWave.

CDU budget breakdown as a diagnostic method for imaging sensitivity in HVM

As leading edge lithography moves to advanced nodes, CDU requirements have relatively increased with technologies 14nm/20nm and beyond. In this paper, we want to introduce the methodology to offer an itemized CDU budget such as Intra-field, Inter-field, wafer to wafer as well as scanner contributors vs. non-scanner contributors (including detailed analysis of reticle contributors like CD, absorber thickness and SWA variation) through Top-Down CDU and Bottom-Up CDU budget breakdown and deliver sources of CD variation with measureable value so that we can estimate CDU gain from them. The test vehicle being used in this experiment is designed based on 14nm D/R basis. Measurement structures are densely located in the slit/scan direction on the reticle for the data collection plan. Hence, we can expand on this methodology to build up the tool reference fingerprint when we release new tool fleet. The final goal will be to establish a methodology for CDU budget breakdown that can be used to draw a conclusion on the root causes of the observed CDU, propose its improvement strategy and estimate the gain.