Eldar Zianbetov

All-digital PLL array provides reliable distributed clock for SOCs

This brief addresses the problem of clock generation and distribution in globally synchronous locally synchronous chips. A novel architecture of clock generation based on network of coupled all-digital PLLs is proposed. Solutions are proposed to overcome the issues of stability and undesirable synchronized modes (modelocks) of high-order bidirectional PLL networks. The VLSI implementation of the network is discussed in CMOS65 nm technology and the simulation results prove the reliability of the global synchronization by the proposed method.

Design and VHDL modeling of all-digital PLLs

In this paper, a VHDL model of a second-order all-digital phase-locked loop (ADPLL) based on bang-bang phase detectors is presented. The developed ADPLL is destined to be a part of a distributed clock generators based on networks of the ADPLL. The paper presents an original model and architecture of a digital multi-bit phase-frequency detector (PFD), and describes in details the VHDL modeling of metastability issues related with asynchronous operation of the digital PFD. This particular architecture of the digital PHD is required by the synchronised operation of the ADPLL network in the context of distributed clock generator. The whole ADPLL model have been validated by purely behavioral (VHDL) and mixed simulation, in which the digital PFD detector was represented by its transistor-level model.

A Digitally Controlled Oscillator in a 65-nm CMOS process for SoC clock generation

This paper presents a CMOS 1.1–2.8 GHz 10 bits digitally controlled oscillator (DCO) for high speed clocking of SoCs. The DCO includes only 269 tuning cells, which is possible thanks to an original algorithm based on weighted combined thermometer code, used for the DCO frequency control. The control circuit of the DCO includes only binary-to-thermometer decoders: that was possible with the proposed technique of virtual extension of number of the DCO ring. It was implemented in 65-nm CMOS technology, with semi-custom layout design allowed to optimize the area on silicon. The design was validated by transistor-level ELDO extracted schematic simulation. Oscillator shows a good linearity in the frequency tunning range, with average power consumption 6mW/GHz with 1.1V supply voltage. Typical phase noise with 1MHz offset and 2GHz carrying frequency is −86.12dBc/Hz.

Distributed clock generator for synchronous SoC using ADPLL network

This paper presents a novel architecture of on-chip clock generation employing a network of oscillators synchronized by the distributed all-digital PLLs (ADPLLs). The implemented prototype has 16 clocking domains operating synchronously in a frequency range of 1.1-2.4 GHz. The synchronization error between the neighboring clock domains is less than 60 ps. The fully digital architecture of the generation offers flexibility and efficient synchronization control suitable for use in synchronous SoCs.

FPGA implementation of reconfigurable ADPLL network for distributed clock generation

This paper presents an FPGA platform for the design and study of network of coupled All-Digital Phase Locked Loops (ADPLLs), destined for clock generation in large synchronous System on Chip (SoC). An implementation of a programmable and reconfigurable 4×4 ADPLL network is described. The paper emphasizes the difference between the FPGA and ASIC-based implementation of such a system, in particular, implementation of digitally controlled oscillators and phase-frequency detector. The FPGA-implemented network allows studying complex phenomena related to coupled ADPLL operation and exploiting stability issues and nonlinear behavior. A dynamic setup mechanism has been proposed for the network, allowing selecting the desirable synchronized state. Experimental results demonstrate the global synchronization of network and performance of the network for different configurations.

A reconfigurable distributed architecture for clock generation in large many-core SoC

This paper focuses on clock generation and distribution in large SoC. After a brief analysis of diverse existed approaches, we propose a distributed architecture based on coupled local clock generators. Three prototypes are presented to demonstrate the feasibility of a large globally synchronous SoC with high reliability by using this approach. Moreover, the reconfigurability feature of this architecture provides a platform for exploring topologies with potentially improved performance.

A design approach for networks of Self-Sampled All-Digital Phase-Locked Loops

This paper addresses the problem of the stability and the performance analysis of N-nodes cartesian networks of self-sampled all digital phase-locked loops. It can be demonstrated that under certain conditions (such as proper filter coefficient values), a global and a local synchronization can be obtained. Our approach to find the optimal conditions consists of analyzing a corresponding linear average system of the cartesian network rather than constructing a piecewise-linear system which is extremely difficult to analyse. The constructed corresponding system takes into account the non-linearity of the network and especially the self-sampling property. It is then analyzed by linear performance criteria such as modulus margin to guarantee a robust stability of the cartesian network. The reliability of our approach is proved by transient simulations in networks of different sizes.

“Swimming pool”-like distributed architecture for clock generation in large many-core SoC

Synchronization is an issue of significant importance in large-scale, distributed and high-speed systems. Traditional globally synchronous approach is no longer viable due to severe wire delay. Solutions such as “Globally Asynchronous, Locally Synchronous (GALS)” approaches suffer from metastability risk limiting their use in many-core SoC for critical applications, such as aerospace, military or medical equipment. This paper presents a distributed clock generator based on a network of oscillators. A great advantage of this architecture is its high stability and immunity to perturbations. This architecture also makes possible to design large fully synchronous SoC. A 10×10 network supplying clock sources for 100 clock domains has been modeled in VHDL and is under design in silicon. Simulation results show ± 40 ps peak-to-peak phase error between two neighboring clock signals and ± 50 ps between two clocks in distance.

FPGA prototyping of large reconfigurable ADPLL network for distributed clock generation

In this paper, we present an FPGA modelling of a distributed and synchronized clock generation for different clock domains based on coupled all-digital phase locked loops (ADPLLs). An implementation of a programmable and reconfigurable 10 ×10 ADPLL network is described, designed for prototyping distributed clock generation in large synchronous system on chip (SoC). The paper emphasizes the reconfigurability of proposed system, which allows exploiting stability issues and nonlinear behavior of a N × M network of coupled oscillators (the dimension can be configured from 1 × 1 to 10 × 10). Configurations with different parameters are compared and analyzed. A dynamic setup mechanism is proposed, allowing selecting the desired synchronized state. Experimental results validate theoretical analysis about circuit parameters and demonstrate the global synchronization of network and performance for different configurations.

Discrete-time modelling and experimental validation of an All-Digital PLL for clock-generating networks

In this paper, we derive a mathematical model of an All-Digital Phase-Locked Loop (ADPLL) employing a time-to-digital phase detector. The model we suggest represents a nonlinear discrete-time map and provides significant benefits for the simulation of a single PLL, a network of PLLs or their design. In particular, the model allows us to take into account the jitter of the reference and local clocks and other noises. The mathematical model (the map) is then compared with a behavioural model implemented in MATLAB Simulink and displays identical results. The simulation of the mathematical and behavioural models are further compared with experimental measurements of a 65nm CMOS ADPLL and show a good agreement.