Elena Ioana Vatajelu

SRAM soft error rate evaluation under atmospheric neutron radiation and PVT variations

In current technologies, the robustness of Static Random Access Memories (SRAM) has to be investigated under any possible source of disturbance. In this paper, we evaluate the reliability of an SRAM cell exposed to atmospheric neutron radiation, affected by random threshold voltage variation and under different operation conditions (supply voltage, process corner and temperature). The SRAM cells Soft Error Rate (SER) at simulation level is estimated using accurate models of atmospheric neutron induced currents. The study shows that in extreme operation conditions and under random process variability, the SER of an SRAM can reach values up to 3X larger than the nominal value, or down to 2X smaller than the nominal value. This large SER range confirms the importance of our study and justifies the need for further evaluation of circuits under radiation at the simulation level.

Analyzing the effect of concurrent variability in the core cells and sense amplifiers on SRAM read access failures

Conventionally, the access failures in SRAMs are treated at core cell level by means of differential bit line voltage analysis. In this work it is shown that under the assumption of random process variability, the conventional approach no longer suffices. It still holds that the differential bit line voltage is degraded by the variability in core cell transistors, but the way this voltage difference is interpreted by the sense amplifier to complete the read operation is influenced by random variability affecting its transistors. Case studies show how variability affecting the sense amplifier can degrade or improve its ability to read the data stored by the core cell, which is itself affected by variability. Using principal component analysis and the SB-SI method, we performed a parametric analysis of the sense amplifier/core cell system and we evaluated the joint probability of access failure. A three times increase in the failure probability has been observed when compared to cells failure probability. Also, the minimum variability value for which a failure is observed is ~2.5X smaller when joint variability is assumed compared to the case when only the core cell is affected by variability.

On the correlation between Static Noise Margin and Soft Error Rate evaluated for a 40nm SRAM cell

Technology scaling has brought forth major issues related to process variation such as circuit stability and reliability degradation, which are especially problematic for the Static Random Access Memories (SRAM). An accurate and fast estimation of memory reliability is required to ensure its correct operation under extreme conditions. For this reason, several metrics have been proposed, such as the Static Noise Margin (SNM), to evaluate the stability of the SRAM cell under static noise; and the Soft Error Rate (SER), to evaluate the reliability of the memory under radiation. While accurate in predicting the memory reliability, the cells SER estimation requires lengthy simulations for each cell configuration. On the other hand, a single simulation is necessary to estimate its SNM. For this reason, in this paper we analyze the possibility of using the classical SNM as a first estimator of SRAM cells reliability under neutron radiation while its transistors are affected by random threshold voltage (Vth) variation. A study based on stability sensitivity analysis to Vth variations leads to a new way of evaluating the SNM metric used to achieve high correlation between SNM and SER.

Reliability analysis of MTJ-based functional module for neuromorphic computing

The power and reliability issues of todays memories limit the improvements attained by their implementation in scaled technology nodes. Several emergent memory technologies attempt to address the technical constraints of todays memories, amongst which, one of the most promising solutions is the Spin-Transfer-Torque Magnetic Random Access Memories (STT-MRAMs). One of the great advantages of the emerging memories is that they favor increasing system complexity and performance. New applications and computation paradigms, such as neuromorphic computing, unfeasible a few years back due to technological limitations, can take profit from this technology. Intensive research has been conducted recently related to magnetic device physics and its implementation as dedicated hardware for neuromorphic computing, however, little work has been conducted to evaluate the reliability of such circuits. In this paper we investigate the effect of meaningful MTJ reliability issues on the behavior of an MTJ-based Spiking Neural Network.

Memristive devices: Technology, design automation and computing frontiers

The memristor is an emerging technology which is triggering intense interdisciplinary activity. It has the potential of providing many benefits, such as energy efficiency, density, reconfigurability, nonvolatile memory, novel computational structures and approaches, massive parallelism, etc. These characteristics may lead to deeply revise existing computing and storage paradigms. This paper presents a comprehensive overview of memristor technology and its potential to design a new computational paradigm.

Challenges and Solutions in Emerging Memory Testing

The research and prototyping of new memory technologies are getting a lot of attention in order to enable new (computer) architectures and provide new opportunities for todays and future applications. Delivering high quality and reliability products was and will remain a crucial step in the introduction of new technologies. Therefore, appropriate fault modelling, test development and design for testability (DfT) is needed. This paper overviews and discusses the challenges and the emerging solutions in testing three classes of memories: 3D stacked memories, Resistive memories and Spin-Transfer-Torque Magnetic memories. Defects mechanisms, fault models, and emerging test solutions will be discussed.

Test and reliability in approximate computing

This paper presents an overview of approximate computing, from the perspective of a test/reliability engineer. The focus of this paper is not on the actual conception of approximate hardware/software/algorithms, but on how specific methods for test and reliability can be used to improve the characteristics (power consumption, area, life expectancy, precision) of approximate computing.

Analyzing resistive-open defects in SRAM core-cell under the effect of process variability

Functional operations of a Static Random Access Memory (SRAM) are strongly affected by random variability in core-cell transistors and by the variability-induced threshold voltage mismatch between the transistors of the Input-Output (IO) circuitry (especially Sense Amplifiers). This variability also affects the faulty behavior of the SRAM array. This paper is focused on the analysis of static and dynamic faults due to resistive-open defects in the SRAM core-cell, taking into account the effects of random process variability in core-cells and IO circuitry. Statistical analyses have been performed to evaluate the SRAM failure probabilities accounting for defects at each possible location. The results show that random process variability in the SRAM core-cell and IO circuitry have an important effect on the behavior of an SRAM array and also on the defect coverage of various commonly-used test sequences. It is shown that under variability, the minimum defect size detected with maximum probability is more than 2X larger than the minimum size detected in nominal conditions, thus leaving a large range of defects undetected. Several stress conditions during test have been evaluated to assess their capability to increase the defect coverage under random process variability.

Test and Reliability in Approximate Computing

This paper presents an overview of test and reliability approaches for approximate computing architectures. We focus on how specific methods for test and reliability can be used to improve the characteristics of approximate computing in terms of power consumption, area, life expectancy and precision. This paper does not address specification and design of approximate hardware/software/algorithms, but provides an in-depth knowledge on how the reliability and test related techniques can be efficiently used to maximize the benefits of approximate computing.

Fully-connected single-layer STT-MTJ-based spiking neural network under process variability

The power, reliability and technological issues of todays memories have led to intensive research of emergent memory technologies and emerging computing paradigms. One of the most promising emerging technology solution is the Spin-Transfer-Torque Magnetic Random Access Memories (STT-MRAMs). It has the great advantage of favoring increasing system complexity and performance, while being CMOS compatible. Computation paradigms, such as neuromorphic computing, unfeasible a few years back due to technological limitations, can take profit from this technology. In this paper we investigate the effect of meaningful MTJ reliability issues on the behavior of a fully-connected, single layer, MTJ-based Spiking Neural Network designed for character recognition.