Mounir Benabdenbi

CAS-BUS: A Test Access Mechanism and a Toolbox Environment for Core-Based System Chip Testing

As System on a Chip (SoC) testing faces new challenges, some new test architectures must be developed. This paper describes a Test Access Mechanism (TAM) named CAS-BUS that solves some of the new problems the test industry has to deal with. This TAM is scalable, flexible and dynamically reconfigurable. The CAS-BUS architecture is compatible with the IEEE P1500 standard proposal in its current state of development, and is controlled by Boundary Scan features.This basic CAS-BUS architecture has been extended with two independent variants. The first extension has been designed in order to manage SoC made up with both wrapped cores and non wrapped cores with Boundray Scan features. The second deals with a test pin expansion method in order to solve the I/O bandwidth problem. The proposed solution is based on a new compression/decompression mechanism which provides significant results in case of non correlated test patterns processing. This solution avoids TAM performance degradation.These test architectures are based on the CAS-BUS TAM and allow trade-offs to optimize both test time and area overhead. A tool-box environment is provided, in order to automatically generate the needed component to build the chosen SoC test architecture.

Configurable serial fault-tolerant link for communication in 3D integrated systems

Three-dimensional (3D) Thru-Silicon-Via (TSV) integration is emerging as a key enabling technology for future high performance systems. The TSV manufacturing defect rates lead to significant interconnect yield loss. For intra-die and inter-die interconnects, techniques such as via widening, via spreading and spare via insertion have been successfully used to improve the yield. However, for high fault rates these solutions are less effective and lead to unacceptable overheads. In this paper, configurable serial fault tolerant links are proposed for inter-die communication in 3D integrated systems. For high TSV fault rates, serial data transmission and signal remapping on fault-free wires are jointly used to ensure correct data transmission. After the interconnect tests, if faulty wires are detected then the link serializes data transmission such that only fault free wires are used. In the proposed link, any subset of data bits can be mapped on any subset of functional wires. Selecting a threshold serialization rate above which the link fails, enables optimal link designs that target interconnect technologies with high fault rates. The impact of inter-die configurable serial fault tolerant links on the performance and area overheads of 3D mesh networks-on-chip (3D NoC) is analyzed. The results show that for an 80% interconnect fault rate the latency degradation up to 14% and area overheads go up to 30%.

Configurable Thru-Silicon-Via interconnect Built-In Self-Test and diagnosis

Three-dimensional integration is a key technology for systems whose performance / power requirements cannot be achieved by traditional silicon technologies. Testing is one of the major challenges of 3D integration. This paper proposes a configurable Interconnect Built-In Self-Test (BIST) technique for inter-die interconnects (Thru-Silicon Vias TSVs). The proposed technique accounts for faults like opens and shorts and also delay faults due to crosstalk. In the proposed fault model, the signal transitions on victim TSVs are affected by the transitions on the aggressor TSVs. The Kth Aggressor Fault model (KAF) assumes that the aggressors of each victim TSV are the K-order neighbors. The test times are reduced as more victim TSVs are concurrently tested. The neighboring order K is technology dependent and it is determined such that the test times are minimal without loss in fault coverage. The proposed BIST has lower area than existing interconnect BIST solutions, while the configuration capabilities increase the area by up to 80%. However, due to relative high TSV pitch (10s μm), the area overheads are small.

On-the-Field Test and Configuration Infrastructure for 2-D-Mesh NoCs in Shared-Memory Many-Core Architectures

This paper addresses the important issue of fault tolerance in network-on-chip (NoC) and presents an on-the-field test and configuration infrastructure for a 2-D-mesh NoC, which can be used in many generic shared-memory many-core tiled architectures and MPSoCs. This paper also details all the hardware and software means needed to: 1) initialize the NoC in a clean state (self-deactivation of faulty NoC components using a controlled built-in self-test strategy) and 2) set up a distributed collaborative configuration infrastructure that can be used to make the chip autonomously determine, during its initialization, the operational degraded architecture, identify and bypass black holes. Experimental results prove that the approach is effective and lightweight in terms of additional software and hardware resources.

Kth-Aggressor Fault (KAF)-based Thru-Silicon-Via Interconnect Built-In Self-Test and Diagnosis

Three-dimensional (3D) integration is a key technology for systems whose performance and power requirements cannot be achieved by traditional silicon technologies. 3D chips consist of two or more stacked silicon dies connected by short inter-die wires called Thru-Silicon-Vias (TSVs). Despite its potential, the poor reliability and yield, thermal management and testing issues remain major challenges of 3D integration. We address the TSV interconnect test challenge of 3D chips by using Interconnect Built-In Self-Test (IBIST) techniques. The proposed test strategy must sensitize structural faults like opens and shorts, and delay faults due to crosstalk. A possible approach is the well-known Maximum Aggressor Fault (MAF) model. Unfortunately, this model is too conservative and it leads to long test sequences and non-negligible hardware costs. Therefore, we present an alternative solution: the Kth-Aggressor Fault (KAF) model. In our model, aggressors of victim wires are neighboring wires within an optimized distance order K. The aggressor order K is technology-dependent and is determined such that the test times are minimal and the fault coverage is maximal. KAF-based IBIST implementation targeting TSV tests occupies three times less area than similar MAF-/marching-based implementations. We also propose a reconfigurable KAF-based IBIST implementation where tests can be performed using different aggressor orders K. Although the reconfigurable IBIST area is significant, interconnect tests during system lifetime can be performed using lower aggressor orders, reducing test duration and improving TSV availability.

CSL: Configurable Fault Tolerant Serial Links for Inter-die Communication in 3D Systems

Three dimensional (3D) integrated systems become a reality nowadays, as Thru-Silicon-Via (TSV) technologies mature. 3D integration promises significant performance and energy efficiency improvements by reducing the signal travel distances and integrating more capabilities on a single chip. High integration costs, thermal management, and poor reliability and yield are major challenges of TSV based 3D chips. High structural and parametric fault rates due to manufacturing defects makes it difficult to achieve high interconnect yield using only spare-based repair solutions. In this paper we address the TSV yield issue by implementing the inter-die links of 3D chips as Configurable fault-tolerant Serial Links (CSLs). When there are not enough available functional TSVs, faults are tolerated by performing data serialization. CSLs help reduce chip costs by improving the TSV yield with very few or no spares at all. For 3D Networks-on-Chip (3D NoCs) we show that the CSL yield improvement comes with moderate area overheads (~12–26%) and small performance penalties (less than 5% average latency overhead).

STEPS: experimenting a new software-based strategy for testing SoCs containing P1500-compliant IP cores

This paper presents STEPS, an innovative software-based approach for testing P1500-compliant SoCs. STEPS is based on the concept that the ATE is not considered as an initiator applying vectors to the SoC test pins but rather as a target, a huge repository of 32-bits test data and control commands. The ATE is connected to the functional SoC external RAM controller interface. The only additional test component in the SoC is a P1500 test processor that converts test data into serial P1500 streams. This paper applies the STEPS methodology to SoCs containing a VCI-compliant interconnect, a microprocessor, P1500-compliant IP cores and an external RAM controller interface. Using the ITC02 SoC benchmarks, a comparison is done between the STEPS architecture and a classical bus-based strategy.

Fault-tolerant adaptive routing under an unconstrained set of node and link failures for many-core systems-on-chip

An online fault tolerant routing algorithm for 2D mesh Networks-on-Chip is presented in this work. It combines an adaptive routing algorithm with neighbor fault-awareness and a new traffic-balancing metric. To be able to cope with runtime permanent and temporary failures that may result in message corruption, message loss or deadlocks, the routing algorithm is enhanced with packet retransmission and a new message recovery scheme. Simulation results, for various network sizes, different traffic patterns, under an unconstrained number of node and link faults, temporary and/or permanent, demonstrate the scalability and efficiency of the proposed algorithm to tolerate multiple failures likely encountered in deep submicron technologies. As the experiments have shown, the proposed algorithm maintains high reliability of more than 97.68% for a 2D mesh network of 16x16 and in the presence of 384 simultaneous link faults. For the same network and in the extreme scenario of 103 routers being simultaneously faulty, the obtained reliability is more than 93.40%.

BIST for logic and local interconnect resources in a novel mesh of cluster FPGA

This paper presents new Built-In Self-Test (BIST) schemes for fault detection and diagnosis of Basic Logic Element (BLE) and intra-cluster (local) interconnect of a novel mesh of cluster FPGA. The proposed schemes avoid redundant test/diagnosis configurations by merging multiple configurations without losing diagnostic resolution. Efficiency of these schemes is calculated in terms of respective number of test/diagnosis configurations for the new FPGA. Results show that 50 BIST configurations are required for a complete test and diagnosis of the cluster. The testability aspects of this FPGA are explored in comparison with the classic clustered-mesh FPGA of the same parameters.

Fully distributed initialization procedure for a 2D-Mesh NoC, including off-line BIST and partial deactivation of faulty components

In this paper, we present an embedded, at speed, off-line, and fully distributed initialization procedure for 2D-Mesh Network-on-Chip (NoC). This procedure is executed at power boot, and targets the detection and the deactivation of the faulty routers and/or faulty communication channels. The final objective is fault tolerance. The proposed procedure is able to clean the NoC from all destructive malfunctions induced by permanent hardware failures. This initialization procedure has been implemented in a reconfigurable version of the DSPIN micro-network, and evaluated from the point of view of Stuck-at fault coverage, and area overhead.