Eleonora Franchi Scarselli

Active Electrode IC for EEG and Electrical Impedance Tomography With Continuous Monitoring of Contact Impedance

The IC presented integrates the front-end for EEG and Electrical Impedance Tomography (EIT) acquisition on the electrode, together with electrode-skin contact impedance monitoring and EIT current generation, so as to improve signal quality and integration of the two techniques for brain imaging applications. The electrode size is less than 2 cm2 and only 4 wires connect the electrode to the back-end. The readout circuit is based on a Differential Difference Amplifier and performs single-ended amplification and frequency division multiplexing of the three signals that are sent to the back-end on a single wire which also provides power supply. Since the systems CMRR is a function of each electrodes gain accuracy, an analysis is performed on how this is influenced by mismatches in passive and active components. The circuit is fabricated in 0.35 μm CMOS process and occupies 4 mm2, the readout circuit consumes 360 μW, the input referred noise for bipolar EEG signal acquisition is 0.56 μVRMS between 0.5 and 100 Hz and almost halves if only EEG signal is acquired.

Power-Aware Job Scheduling on Heterogeneous Multicore Architectures

This paper presents a power-aware scheduling algorithm based on efficient distribution of the computing workload to the resources on heterogeneous CPU-GPU architectures. The scheduler manages the resources of several computing nodes with a view to reducing the peak power. The algorithm can be used in concert with adjustable power state software services in order to further reduce the computing cost during high demand periods. Although our study relies on GPU workloads, the approach can be extended to other heterogeneous computer architectures. The algorithm has been implemented in a real CPU-GPU heterogeneous system. Experiments prove that the approach presented reduces peak power by 10 percent compared to a system without any power-aware policy and by up to 24 percent with respect to the worst case scenario with an execution time increase in the range of 2 percent. This leads to a reduction in the system and service costs.

A Driving Right Leg Circuit (DgRL) for Improved Common Mode Rejection in Bio-Potential Acquisition Systems

The paper presents a novel Driving Right Leg (DgRL) circuit designed to mitigate the effect of common mode signals deriving, say, from power line interferences. The DgRL drives the isolated ground of the instrumentation towards a voltage which is fixed with respect to the common mode potential on the subject, therefore minimizing common mode voltage at the input of the front-end. The paper provides an analytical derivation of the common mode rejection performances of DgRL as compared to the usual grounding circuit or Driven Right Leg (DRL) loop. DgRL is integrated in a bio-potential acquisition system to show how it can reduce the common mode signal of more than 70 dB with respect to standard patient grounding. This value is at least 30 dB higher than the reduction achievable with DRL, making DgRL suitable for single-ended front-ends, like those based on active electrodes. EEG signal acquisition is performed to show how the system can successfully cancel power line interference without any need for differential acquisition, signal post-processing or filtering.

Electronic Microsystems for Handling of Rare Cells

This review paper summarizes some of the most challenging issues regarding the development of electronic microsystems for the isolation, manipulation, and characterization of rare cells. Two relevant areas, namely, immunology for cancer therapy and monitoring of microbial contaminants in water, are presented as example applications which require handling of rare cells. Starting from these applications, the state of the art in electronic microsystem research is presented, and various solutions are discussed, highlighting the advantages and disadvantages of each technology and suggesting the need to integrate multiple solutions to meet the application requirements.

A Long-Distance RF-Powered Sensor Node with Adaptive Power Management for IoT Applications

We present a self-sustained battery-less multi-sensor platform with RF harvesting capability down to −17 dBm and implementing a standard DASH7 wireless communication interface. The node operates at distances up to 17 m from a 2 W UHF carrier. RF power transfer allows operation when common energy scavenging sources (e.g., sun, heat, etc.) are not available, while the DASH7 communication protocol makes it fully compatible with a standard IoT infrastructure. An optimized energy-harvesting module has been designed, including a rectifying antenna (rectenna) and an integrated nano-power DC/DC converter performing maximum-power-point-tracking (MPPT). A nonlinear/electromagnetic co-design procedure is adopted to design the rectenna, which is optimized to operate at ultra-low power levels. An ultra-low power microcontroller controls on-board sensors and wireless protocol, to adapt the power consumption to the available detected power by changing wake-up policies. As a result, adaptive behavior can be observed in the designed platform, to the extent that the transmission data rate is dynamically determined by RF power. Among the novel features of the system, we highlight the use of nano-power energy harvesting, the implementation of specific hardware/software wake-up policies, optimized algorithms for best sampling rate implementation, and adaptive behavior by the node based on the power received.

EEG acquisition system based on active electrodes with common-mode interference suppression by Driving Right Leg circuit.

We present a system for the acquisition of EEG signals based on active electrodes and implementing a Driving Right Leg circuit (DgRL). DgRL allows for single-ended amplification and analog-to-digital conversion, still guaranteeing a common mode rejection in excess of 110 dB. This allows the system to acquire high-quality EEG signals essentially removing network interference for both wet and dry-contact electrodes. The front-end amplification stage is integrated on the electrode, minimizing the systems sensitivity to electrode contact quality, cable movement and common mode interference. The A/D conversion stage can be either integrated in the remote back-end or placed on the head as well, allowing for an all-digital communication to the back-end. Noise integrated in the band from 0.5 to 100 Hz is comprised between 0.62 and 1.3 μV, depending on the configuration. Current consumption for the amplification and A/D conversion of one channel is 390 μA. Thanks to its low noise, the high level of interference suppression and its quick setup capabilities, the system is particularly suitable for use outside clinical environments, such as in home care, brain-computer interfaces or consumer-oriented applications.

A 40 nm CMOS I/O Pad Design With Embedded Capacitive Coupling Receiver for Non-Contact Wafer Probe Test

A receiver for capacitive coupled communication is embedded in a digital input/output pad to add the capacity for non-contact data communication, while maintaining size, ESD protection, and buffering functions unchanged, even in contact mode. The added feature allows non-contact probing of die pads and provides a reliable alternative solution to mechanical probing for electrical wafer sort testing of Systems-on-Chip (SoC) and Systems-in-Package (SiPs) because of elimination of pad damage and reduction of the force required to create stable electrical contacts between probe needles and pads. The proposed receiver detects the displacement current flowing through the capacitive channel created between the connecting probe needle and top metal pad surface when a transition in the input digital stimulus signal occurs. The receiver is designed to work up to 100 Mbit/s data rate with a power of 340 μW in a 40 nm CMOS process. The circuit trade-offs between frequency, amplitude of the step input and distance are discussed. Experimental results show that for a 5 V input voltage amplitude, the receiver allows correct data transmission at a distance up to 5 μm, which increases to 10 μm if the top aluminum layer is divided in two, using a customized I/O pad design. The feasibility of this non-contact testing approach was verified through electrical tests on two IP blocks, an LFSR, and a PLL with a scan chain, using a standard prober and a cantilever probe card designed with 19 needles of different lengths to enable both physical contact connections for power supply and non-contact capacitive coupling data communication for signals.

Design-space exploration of an eFPGA soft-core based on Multi-Stages Switching Networks

Embedded FPGAs are becoming appealing IPs to enhance modern SoCs, since technology scaling is enabling reconfigurability at lower area impact. This notwithstanding, to become effective eFPGAs should be highly adaptable to support application-specific optimization, in terms of DSP blocks, technology options and floorplan requirements. For that, in this paper, we analyse a soft-core eFPGA template based on Multi-Stage Switching Network which couples high flexibility with a modular design approach based on the regular replication of few simple switch modules for the programmable routing. Implementation on 65nm technology showed the existence of a significantly wide design space which allows to quickly optimize the device for area, speed and/or leakage power. Results show that depending on architectural and technology options adopted, performance can vary in terms of area (~50%), speed (+/-30%) and leakage (~90%) with respect to a reference design.

Parallel Solver for Diffuse Optical Tomography on Realistic Head Models With Scattering and Clear Regions

Diffuse optical tomography is an imaging technique, based on evaluation of how light propagates within the human head to obtain the functional information about the brain. Precision in reconstructing such an optical properties map is highly affected by the accuracy of the light propagation model implemented, which needs to take into account the presence of clear and scattering tissues. We present a numerical solver based on the radiosity-diffusion model, integrating the anatomical information provided by a structural MRI. The solver is designed to run on parallel heterogeneous platforms based on multiple GPUs and CPUs. We demonstrate how the solver provides a 7 times speed-up over an isotropic-scattered parallel Monte Carlo engine based on a radiative transport equation for a domain composed of 2 million voxels, along with a significant improvement in accuracy. The speed-up greatly increases for larger domains, allowing us to compute the light distribution of a full human head (≈ 3 million voxels) in 116 s for the platform used.

Soft-Core Embedded-FPGA Based on Multistage Switching Networks: A Quantitative Analysis

Embedded field programmable gate arrays (eFPGA) can provide modern systems-on-a-chip (SoCs) with the flexibility required to face the growth of nonrecurring engineering and manufacturing costs. On the other hand, SoC designers usually perceive eFPGAs as area-hungry IPs with poor flexibility in terms of performance, power and area tradeoff since they are typically available as custom-designed hard macros. In this scenario, technology scaling is allowing designers to reduce the impact of the eFPGA area gap, while effective exploitation of all the technology options (e.g., the transistor threshold) entails moving toward soft-core eFPGAs to match specific application needs. In this paper, we propose an look-up table-based soft-core eFPGA featuring a synthesizable and parametric architecture. A key point of our proposal is that we have adopted a multistage switching network (MSSN) to implement the programmable interconnect, since this ensures a synthesizable and congestion-free architecture. Quantitative evaluation of our eFPGA shows a significantly wide design-space available on very different technologies (we experimented STMicroelectronics CMOS 65 nm and BCD9s 0.11 μm). Application-driven evaluation showed how for a fixed eFPGA size (i.e., number of logic blocks) different configurations of the MSSN allow designers to speed up performance by 20/60%, as well as to maximize the computational density for a given area budget.