Eli Rosenberg

A 15 MHz 32-channel flash ADC FASTBUS board for use at LEP

The design and performance of a single-width multilayer FASTBUS board for digitization of electromagnetic calorimeter data at LEP are described. The board consists of 32 channels of flash analog-to-digital converters (ADCs) clocked at 15 MHz. The digitized data are filtered through a zero-suppression circuit, stored in a buffer memory, and then reformatted using an onboard microprocessor. The microprocessor allows calibration tasks such as pedestal monitoring and linearity/relative gain measurements to be performed efficiently. >

The DELPHI Barrel Electromagnetic Calorimeter Flash ADC Based Digitizer

We describe the design and performance of an 8-bit Flash ADC based readout system developed for use on the cathode pads of the DELPHI High Density Projection Chamber (HPC). A dynamic range of 800:1 is obtained at input frequencies of 15 MHz using a bilinear voltage divider reference chain. Performance characteristics of the digitizing circuits for a CAMAC version of this readout system are presented. The design of a FASTBUS version is presented.

Performance of flash ADCs in the 100 MHz range. II. Results from 8 bit devices

For pt.I see ibid., vol.38, p.102 (1991). Using a test bench that was previously described, the authors have performed tests on 8-b flash analog-to-digital converters (ADCs). For each device they have measured parameters such as linearity, number of effective bits, noise level, aperture jitter, integral and differential nonlinearity, analog bandwidth, and total harmonic distortion. The tests were characterized according to input signal. The tests consisted of sampling the input waveform by taking an event record of up to 2048 consecutive digitizations and then applying the appropriate analysis to this event record. The test results are given. >

Performance of flash ADCs in the 100 MHz range. I. Test bench and preliminary results

Describes a systematic study of the performance of commercially available FADCs (flash analog-to-digital converter) in the 100-megasample/s range, which might be suitable for use at the Superconducting Super Collider. Performance characteristics are measured using a CAMAC-based test bench. Among the FADC performance characteristics reported are linearity, differential linearity, and the effective number of bits. >

Testing ADC's at sample rates from 20 to 120 MSPS

Results are presented from an ongoing program to test the performance of high-speed analog-to-digital converters suitable for use at the Superconducting Super Collider (SSC) and Large Hadron Collider (LHC). For each device a large number of parameters is measured, such as number of effective bits, noise level, aperture jitter, nonlinearity, analog bandwidth, and total harmonic distortion. Results from a variety of 8-b and 10-b devices are presented. >

Design and Performance of a CCD Based Readout for the Delphi Barrel Electromagnetic Calorimeter

We describe the design criteria and performance of a CCD based readout system developed for use in the DELPHI experiment at LEP. These circuits are designed for use on the cathode pads of the High Density Projection Chamber (HPC) which will serve as the DELPHI central region electromagnetic calorimeter. Two separate CAMAC versions of this system have been tested on prototype HPC modules exposed to both hadrons and electrons. Stability and performance characteristics of these circuits at CCD input frequencies up to 20 MHz are presented. We also present results on the electron shower energy resolution for the HPC prototypes.

A Microprocessor Based CAMAC Data Acquisition System for Use in High Energy Physics

A high energy physics CAMAC data acquisition system is described which consists of a Motorola 68000 microprocessor monoboard system interfaced to two Digital Equipment Corporation (DEC) UNIBUSes. The system can be replicated any number of times (n) as a peripheral device on a host UNIBUS. This allows for n parallel channels of DMA data acquisition on n auxiliary UNIBUSes each with a CAMAC branch driver and 256 Kbytes of memory. Thus, the system reduces the time required to acquire data by a factor of ~n and simultaneously increases the total memory buffer available to the host UNIBUS by a factor of n. Such a technique is useful at fixed target particle accelerators where data is collected at a high instantaneous rates for a small fraction (10-25%) of the overall cycle time.

Testing fast ADC's at sample rates between 20 and 140 MSPS

The performance of high-speed analog-to-digital converters (ADCs) suitable for use at the Superconducting Super Collider and the Large Hadron Collider has been tested. A test bench has been built to evaluate the performance of ADCs in the range of sampling rates from 20 to 240 megasamples per second (MSPS), thus permitting tests of devices under identical conditions and with identical parameter definitions. For each device, a large number of parameters have been measured, such as number of effective bits, noise level, aperture jitter, integral and differential nonlinearity, analog bandwidth, and total harmonic distortion. The authors describe some of the lessons learned from this test program and present results on a range of eight and ten bit devices.<<ETX>>

ARTEMIS: a VMS based Fastbus module testing and evaluation system

A flexible Fastbus module testing and evaluation system is described. It has been developed in conjunction with the Ames Waveform Digitizer being used in the DELPHI experiment at LEP (Large Electron Positron Collider). The system hardware includes a DEC MicroVAX II (or equivalent) running microVMS with Fastbus and GPIB instrumentation buses. The software is menu driven, makes extensive use of the screen management routines of the VAX/VMS system, and is designed for easy modification. In a period of about four months, 600 Fastbus modules currently in use in the DELPHI experiment were tested and debugged. >