R. McKay

A 15 MHz 32-channel flash ADC FASTBUS board for use at LEP

The design and performance of a single-width multilayer FASTBUS board for digitization of electromagnetic calorimeter data at LEP are described. The board consists of 32 channels of flash analog-to-digital converters (ADCs) clocked at 15 MHz. The digitized data are filtered through a zero-suppression circuit, stored in a buffer memory, and then reformatted using an onboard microprocessor. The microprocessor allows calibration tasks such as pedestal monitoring and linearity/relative gain measurements to be performed efficiently. >

The DELPHI Barrel Electromagnetic Calorimeter Flash ADC Based Digitizer

We describe the design and performance of an 8-bit Flash ADC based readout system developed for use on the cathode pads of the DELPHI High Density Projection Chamber (HPC). A dynamic range of 800:1 is obtained at input frequencies of 15 MHz using a bilinear voltage divider reference chain. Performance characteristics of the digitizing circuits for a CAMAC version of this readout system are presented. The design of a FASTBUS version is presented.

Performance of flash ADCs in the 100 MHz range. II. Results from 8 bit devices

For pt.I see ibid., vol.38, p.102 (1991). Using a test bench that was previously described, the authors have performed tests on 8-b flash analog-to-digital converters (ADCs). For each device they have measured parameters such as linearity, number of effective bits, noise level, aperture jitter, integral and differential nonlinearity, analog bandwidth, and total harmonic distortion. The tests were characterized according to input signal. The tests consisted of sampling the input waveform by taking an event record of up to 2048 consecutive digitizations and then applying the appropriate analysis to this event record. The test results are given. >

Performance of flash ADCs in the 100 MHz range. I. Test bench and preliminary results

Describes a systematic study of the performance of commercially available FADCs (flash analog-to-digital converter) in the 100-megasample/s range, which might be suitable for use at the Superconducting Super Collider. Performance characteristics are measured using a CAMAC-based test bench. Among the FADC performance characteristics reported are linearity, differential linearity, and the effective number of bits. >

A test bench for evaluating fast ADCs

Abstract This document describes a test bench and procedures used to evaluate the performance of analog-to-digital converters that operate in the range of 10 to 140 million samples per second.

Testing ADC's at sample rates from 20 to 120 MSPS

Results are presented from an ongoing program to test the performance of high-speed analog-to-digital converters suitable for use at the Superconducting Super Collider (SSC) and Large Hadron Collider (LHC). For each device a large number of parameters is measured, such as number of effective bits, noise level, aperture jitter, nonlinearity, analog bandwidth, and total harmonic distortion. Results from a variety of 8-b and 10-b devices are presented. >

CANbus and microcontroller use in the BaBar detector at SLAC

The BaBar collaboration has chosen the Controller Area Network (CAN) bus for its controls and monitoring field bus. In addition, the Motorola MC68HC705X32 microcontroller, which has a CAN interface, was chosen for the standard intelligent device for monitoring boards. This paper describes the CAN system used by BaBar and the embedded software that supports it. The General Monitoring Board (GMB) is presented as a specific example. The GMB is a CAN module that digitizes 32 differential analog signals and has eight bits of bi-directional I/O.

Using IEEE standard 1057 for testing analog-to-digital converters

We have used IEEE Trial Use Standard 1057 since 1989 for testing and evaluating analog-to-digital converters for use in high energy physics experiments. This standard primarily covers waveform digitizers, such as digital oscilloscopes, but much of it is applicable to testing ADCs. Using DC levels and sine, triangle, and specialized waveforms, we measure parameters such as integral and differential nonlinearity, number of effective bits, word error rate, short term settling time, and overvoltage recovery. We summarize the tests performed and describe our experience in using the standard.

Recent results from tests of fast analog-to-digital converters

We present results from tests of eight, ten, and twelve bit ADCs that operate in the range of 10 to 120 megasamples per second. We use a test bench and software we have developed to perform the tests on as wide a range of devices as possible. By testing devices with the same input signals, the same software, and the same parameter definitions, we make possible direct comparisons between competing devices. Important parameters measured include integral and differential nonlinearity, effective number of bits, and word error rate. While the tests are intended primarily to benefit the design of high rate physics experiments, the results are also useful to workers in other fields. >

Results of radiation hardness tests and performance tests of the HS9008RH flash ADC

Results from tests characterizing the performance and radiation hardness of the HS9008RH flash analog to digital convertor (FADC) are presented. These tests were performed primarily to evaluate the suitability of this device for use in the GEM Central Tracker at the SSC experiment. Basic performance characteristics and susceptibility of these characteristics to radiation were examined. Performance test results indicate that the device integral nonlinearity is sampling rate dependent and worsens rapidly above a sampling rate of 15 megasamples per second (MSPS). No degradation in performance of the device was observed after its exposure of up to 81 Mrad of 1.25 MeV /spl gamma/ radiation from a /sup 60/Co source. Exposure of the device to a reactor fast neutron fluence (E>100 keV) of 5/spl times/10/sup 14//cm/sup 2/ resulted in no significant observed performance degradation as well. >