Elke Erben

Structural properties of as deposited and annealed ZrO2 influenced by atomic layer deposition, substrate, and doping

Thin ZrO2 films are of high interest as high-k material in dynamic random access memory (DRAM), embedded dynamic random access memory, and resistive random access memory as well as for gate oxides. Actually, ZrO2 is predicted to be the key material in future DRAM generations below 20 nm. Profound knowledge of pure and doped ZrO2 thin films, especially of the structural properties, is essential in order to meet the requirements of future devices. This paper gives a detailed overview about the structural properties of ZrO2 films in dependence of various process parameters. The study of atomic layer deposition (ALD) growth mechanisms of ZrO2 on a TiN-substrate in comparison to a Si-substrate covered with native oxide exhibits significant differences. Furthermore, the structural properties crystallinity, surface roughness, and film stress are studied after the ALD deposition in dependence of the process parameters deposition temperature, layer thickness, and underlying substrate. Remarkable dependencies of the ZrO2 crystallization temperatures on the substrates are figured out. The structural properties after various annealing steps are monitored as well. The influence of doping by SiO2 and Al2O3 is studied, which is primarily used to keep the thin films amorphous during deposition.

TEMAZ/O3 atomic layer deposition process with doubled growth rate and optimized interface properties in metal–insulator–metal capacitors

ZrO2 is of very high interest for various applications in semiconductor industry especially as high-k dielectric in metal–insulator–metal (MIM) capacitor devices. Further improvement of deposition processes, of material properties, and of integration schemes is essential in order to meet the strict requirements of future devices. In this paper, the authors describe a solution to solve one of the key challenges by reducing the process time of the bottle neck high-k atomic layer deposition (ALD). The authors extensively optimized the most common ALD process used for the ZrO2 deposition (TEMAZ/O3) resulting now in a doubled growth rate compared to the published growth rates of maximum 1 A/cycle. Chemical reactions explaining the origin of the high growth rate are proposed by theoretical process modelling. At the same time, the outstanding electrical properties of ZrO2 thin films could be preserved. Finally, the integration of the ZrO2 process in MIM capacitor devices with TiN electrodes was evaluated. Thereb...

Macroscopic and microscopic electrical characterizations of high-k ZrO2 and ZrO2/Al2O3/ZrO2 metal-insulator-metal structures

In order for sub-10 nm thin films of ZrO2 to have a dielectric constant larger than 30 they need to be crystalline. This is done by either depositing the layer at higher temperatures or by a postdeposition annealing step. Both methods induce high leakage currents in ZrO2 based dielectrics. In order to understand the leakage a thickness series of ultrathin ZrO2 and nanolaminate ZrO2/Al2O3/ZrO2 (ZAZ) films, deposited by atomic layer deposition, was investigated. After deposition these films were subjected to different rapid thermal annealing (RTA) processes. Grazing incidence x-ray diffraction and transmission electron microscopy yield that the crystallization of ZrO2 during deposition is dependent on film thickness and on the presence of an Al2O3 sublayer. Moreover, the incorporation of Al2O3 prevents crystallites from spanning across the entire film during RTA. C-V and I-V spectroscopies show that after a 650 °C RTA in N2 the capacitance equivalent oxide thickness of 10 nm ZAZ films is reduced to 1.0 nm w...

Synthesis of SrTiO3 by crystallization of SrO/TiO2 superlattices prepared by atomic layer deposition

An approach for the preparation of homogenous SrTiO3 (STO) thin films with unprecedented compositional control is presented. Nanolaminates of SrO and TiO2 were deposited at 300 °C by atomic layer deposition on bare silicon, as well as on ruthenium electrodes using metalorganic precursors [Ti(NEtMe)4 (TEMATi),Sr(iPr3Cp)2 (AbsoluteSr)]. Care was taken that the individual sublayers were grown with a number of subcycles well in the steady-state growth regime. This enabled linear composition tuning with the Sr:Ti pulse ratio, which is beneficial for process control. Still, a substrate-specific growth behavior was observed for the individual precursors leading to different cycle ratio/composition dependence for samples grown on Si as compared to Ru substrates. This could be attributed to specific nucleation conditions, which are most pronounced for the initial cycle, but also prevail throughout the film. The as-deposited layers are well separated and the sublayers are amorphous. Subsequent furnace-annealing gen...

Fluorine interface treatments within the gate stack for defect passivation in 28 nm high-k metal gate technology

A novel method of fluorine incorporation into the gate dielectric by gaseous thermal NF3 interface treatments for defect passivation have been investigated in 28 nm high-k metal gate technology with respect to improvement in device reliability. The thermal treatment suppresses physical interface regrowth observed in previous plasma-assisted fluorine treatments. Detailed defect characterization by spectroscopic charge pumping is used to characterize the influence of fluorine on trap states in the interfacial oxide layer. Comprehensive structural as well as electrical characterization linked with bias temperature instability measurements indicates the potential of improving reliability in high-k metal gate technology by gaseous introduction of fluorine into the gate dielectric.

Charge transition levels of oxygen, lanthanum, and fluorine related defect structures in bulk hafnium dioxide (HfO2): An ab initio investigation

Intrinsic defect structures and impurity atoms are one of the main sources of leakage current in metal-oxide-semiconductor devices. Using state of the art density functional theory, we have investigated oxygen, lanthanum, and fluorine related defect structures and possible combinations of them. In particular, we have calculated their charge transition levels in bulk m-HfO2. For this purpose, we have developed a new scaling scheme to account for the band gap underestimation within the density functional theory. The obtained results are able to explain the recent experimental observation of a reduction of the trap density near the silicon valence band edge after NF3 treatment and the associated reduction of the device degradation.

Influence of nitrogen trap states on the electronic properties of high-k metal gate transistors

The origin of the defects associated with the nitridation of the interface layer between Si and HfO2 is investigated. The electronic properties change upon nitridation which impact severely the gate capacitance and gate leakage current. We modeled the temperature-dependent leakage current in SiON/HfO2 gate dielectrics for positive and negative gate voltages by means of a multi-phonon trap-assisted tunneling scheme to extract the trap distribution. The results are supported by charge pumping measurements and simulation. To clarify the origin of the additional traps in the SiON interface we performed ab-initio calculation and correlated the results with the gate leakage current measurements. Finally, we shed new light on the relation between stress-induced leakage current and positive bias temperature instability.

Impact of both metal composition and oxygen/nitrogen profiles on p-channel metal-oxide semiconductor transistor threshold voltage for gate last high-k metal gate

As transistor size continues to shrink, SiO2/polySi has been replaced by high-k/metal gate (HKMG) to enable further scaling. Two different HKMG integration approaches have been implemented in high volume production: gate first and gate last—the latter is also known as replacement gate approach. In both integration schemes, getting the right threshold voltage (Vt) for NMOS and PMOS devices is critical. A number of recent studies have shown that Vt of devices is highly dependent on not just the as deposited material properties but also on subsequent processing steps. In this work, the authors developed an advanced high-resolution electron energy loss spectroscopy method capable of accurate measurement of material composition on device structures. Using this method, the nitrogen and oxygen concentration at the HKMG interface on p-channel field-effect transistor (PFET) transistors with slightly different metal gate stacks were studied. The authors demonstrated that the correct amount of nitrogen and oxygen at...

Capacitance Transient Spectroscopy Measurements on High-k Metal Gate Field Effect Transistors Fabricated Using 28nm Technology Node

Fast progress in nanometer-node high-k metal gate (HKMG) technology requires the development of versatile and detailed characterization methods for semiconductor / dielectric / metal stacks and interfaces between them. Complexity of the advanced fabrication processes does not allow preparation of model samples with dimensions used in standard laboratory measurements. In this report we apply capacitance transient spectroscopy measurements for the characterization of HKMG field effect transistors (FET) fabricated in the standard 28 nm node technology. Measurements were performed on n-FET devices. The devices were characterized in the as-fabricated stage, after application of electrical stress and after fluorine implantation introduced to passivate the interface carrier traps. Our results show good correspondence with those obtained by other characterization methods and supply detailed information on the energy distribution of the interface trap density in the system.

Inline-Characterization and Step Coverage Optimization of Deposited Dielectrics in DRAM Structures

A combination of a common ellipsometric thickness determination from a plane surface and volume-related information gained from a Fourier transform infrared measurement enables monitoring of thin nm-scale layers in 3-D structures. This method was established to characterize dielectric layers deposited by atomic layer deposition within a capacitor structure of a 65-nm DRAM technology. The influence of precursor flow and pulse time on the overall homogeneity and step coverage of zirconium aluminum oxide was investigated. A clear correlation to the precursor amount and the geometry of the deposition tool can be shown.