Dina H. Triyoso

Robust PEALD SiN spacer for gate first high-k metal gate integration

As we packed more and more transistors into one chip and as the size of transistor continues to shrink, the need for conformal sidewall protection layer becomes critical. In this work improved device properties is demonstrated using PEALD SiN spacer compared to the conventional PECVD SiN spacer.

Extending HKMG scaling on CMOS with FDSOI: Advantages and integration challenges

High-k metal gate (HKMG) has been implemented in production for nearly 10 years. As scaling of HKMG on bulk Si is reaching its limit, alternative device architecture such as FINFETs and FDSOI are being pursued. FDSOI is well suited for applications needing a balanced trade-off among power, performance and cost, such as the Internet of Things (IoTs). Here we show that compared to HKMG on bulk Si, HKMG FDSOI transistors have less VT variation due to its undoped channel. Furthermore, FDSOI unique back-biasing capability offers additional knob to further reduce VT variation. There are, however, a few challenges that must be overcome for successful integration of FDSOI in CMOS. Those challenges such as preventing thin SOI channel erosion, maintaining strain in channel SiGe, preventing oxygen ingress in gatestack, obtaining a low overlap capacitance and growing raised source/drain epi will be discussed.

Impact of both metal composition and oxygen/nitrogen profiles on p-channel metal-oxide semiconductor transistor threshold voltage for gate last high-k metal gate

As transistor size continues to shrink, SiO2/polySi has been replaced by high-k/metal gate (HKMG) to enable further scaling. Two different HKMG integration approaches have been implemented in high volume production: gate first and gate last—the latter is also known as replacement gate approach. In both integration schemes, getting the right threshold voltage (Vt) for NMOS and PMOS devices is critical. A number of recent studies have shown that Vt of devices is highly dependent on not just the as deposited material properties but also on subsequent processing steps. In this work, the authors developed an advanced high-resolution electron energy loss spectroscopy method capable of accurate measurement of material composition on device structures. Using this method, the nitrogen and oxygen concentration at the HKMG interface on p-channel field-effect transistor (PFET) transistors with slightly different metal gate stacks were studied. The authors demonstrated that the correct amount of nitrogen and oxygen at...

Novel N/PFET Vt control by TiN plasma nitridation for aggressive gate scaling

A novel N/PFET threshold voltage (Vt) control scheme was developed for aggressive gate scaling. TiN plasma nitridation reduces absolute Vt by 100mV for both NFETs and PFETs at the same time without photolithography step increase and performance or reliability penalty. TiN plasma nitridation does not need additional work function metal (WFM) to control Vt and hence allows thicker gate contact metal for low gate resistance and improved AC performance.

Understanding the materials, electrical and reliability impact of Al-addition to ZrO 2 for BEOL compatible MIM capacitors

As operating frequency and circuit density of VLSI systems continue to increase, the L*di/dt induced voltage fluctuations in the power grid increasingly becomes a source of voltage/timing problems. On-chip decoupling capacitors, placed in close proximity to the power grid conductors, can offset parasitic inductances and thereby reduce the high frequency noise. High capacitance density MIM capacitors, placed between the last two metal layers, have been shown to be effective in achieving on-chip decoupling in high performance processors. There have been many reports in the literature on the use of high-k material such as Ta2O5, HfO2, ZrO2 for MIM capacitors [1-5]. A large number of reports of high-k MIM are focused on DRAM rather than decoupling capacitors applications [2-4]. One important difference between the DRAM capacitor module and decoupling capacitors is the thermal budget requirement. DRAM capacitors allow a higher thermal budget (~700°C) compared to embedded decoupling capacitors which must meet the BEOL thermal budget requirement (~400°C). We have recently reported an improved reliability by addition of Al into ZrO2 [6]. In this work, we report detailed material, electrical and further reliability characterization of ZrO2-based MIM capacitor capable of meeting stringent reliability requirement while maintaining compatibility with the backend processing thermal budget. A capacitor with >20fF/μm2 capacitance density and leakage current density <;100nA/cm2 meeting lifetime target (operated on both polarities) is demonstrated.

ALD ZrO 2 processes for BEoL device applications

In this paper three different ZrO2 ALD processes are studied as high-k dielectric in BEoL device applications. One metal organic precursor is compared to a halide precursor used with two different oxidizing agents. The structure, composition and morphology of the films are analyzed on bare Si wafers and the electrical properties such as capacitance, leakage and reliability are investigated on fully integrated BEoL decoupling capacitors. One of the halide ALD processes is identified as the most promising candidate for BEoL capacitor applications.

Impact of precursors choice on characteristics of PEALD SiN for spacer applications

As transistor size continues to shrink, the need for conformal spacer which is insensitive to loading condition arises. Previously we have reported improved device characteristics for transistors with PEALD SiN spacer compared to those with CVD SiN spacer. In this work characteristics of PEALD SiN spacer deposited with liquid or gas precursors is studied. Good device properties are obtained with both precursor types, with slightly better iso-loading characteristics for devices with SiN deposited using liquid precursor.

Characterization of atomic layer deposited low-k spacer for FDSOI high-k metal gate transistor

FDSOI is one of the alternative device architectures chosen to extend CMOS scaling for high-k metal gate. FDSOI is ideal for applications needing a balanced trade-off among power, performance and cost, such as the Internet of Things (IoTs). One of the challenges in FDSOI integration is to obtain a low gate to source drain capacitance (overlap capacitance or DC capacitance). To enable this, low k spacer material is needed. In this study we compared two ALD low-k spacer materials namely SiOCN and SiBCN against the conventional SiN spacer. Material characterization reveals SiOCN has lower etch rate than SiBCN. Both materials have good thermal stability. Transistors with SiOCN and SiBCN spacers were formed. Implementation of low-k spacer does not have significant impact on VT variability and oxygen ingress. Transistors with SiOCN and SiBCN spacer exhibited lower DC and AC capacitance without transistor resistance degradation.

La-doped ZrO 2 based BEoL decoupling capacitors

Presented within this paper is a study on thin La-doped ZrO2 films used as dielectric material in decoupling capacitors in BEoL. The effect of combined atomic layer deposition processes and the integration concept of La are discussed with respect to capacitance density, leakage current, breakdown voltage and reliability. Physical characterization helps to understand the measured parameters. Overall, the La-doping is able to improve the breakdown voltage significantly without degrading reliability, but at the expense of increased capacitance density compared to undoped films.

XPS-XRF hybrid metrology enabling FDSOI process

Planar fully-depleted silicon-on-insulator (FDSOI) technology potentially offers comparable transistor performance as FinFETs. pFET FDOSI devices are based on a silicon germanium (cSiGe) layer on top of a buried oxide (BOX). Ndoped interfacial layer (IL), high-k (HfO2) layer and the metal gate stacks are then successively built on top of the SiGe layer. In-line metrology is critical in precisely monitoring the thickness and composition of the gate stack and associated underlying layers in order to achieve desired process control. However, any single in-line metrology technique is insufficient to obtain the thickness of IL, high-k, cSiGe layers in addition to Ge% and N-dose in one single measurement. A hybrid approach is therefore needed that combines the capabilities of more than one measurement technique to extract multiple parameters in a given film stack. This paper will discuss the approaches, challenges, and results associated with the first-in-industry implementation of XPS-XRF hybrid metrology for simultaneous detection of high-k thickness, IL thickness, N-dose, cSiGe thickness and %Ge, all in one signal measurement on a FDSOI substrate in a manufacturing fab. Strong correlation to electrical data for one or more of these measured parameters will also be presented, establishing the reliability of this technique.