Emi Garcia

Packet classification using adaptive rules cutting (ARC)

This paper introduces an advanced packet classification algorithm called adaptive rules cutting (ARC). In the same way as the HiCuts and HyperCuts Algorithm, ARC is based on cutting the multi-dimensional space into smaller segments for rule reduction. Unlike HiCuts where dividing the region takes more than 1 level, and unlike HyperCuts in which each node represents a k-dimensional hypercube, ARC allows the flexibility of considering all dimensions. This extra degree of freedom and a new set of heuristics allow adaptation for optimum rule cutting for a given amount of storage. Rule cutting simulations and performance studies show that ARC can provide a reduction of up to 98% of the given rules in the first instance.

Improving Key Distribution forWireless Sensor Networks

Key management plays an essential role in achieving security in wireless sensor networks (WSNs). A range of new key distribution schemes have been suggested in an attempt to improve existing ones which are inappropriate for WSNs. However these schemes are still vulnerable when a certain number of sensor nodes are captured. The key distribution proposed in this paper makes use of coordinator sensor nodes, increasing the number of nodes that would need to be captured by an adversary. The analysis of our scheme against well known schemes such as the DDHV scheme shows a significant improvement in security.

Path-Key Establishment for Wireless Sensor Networks

Wireless sensor networks are composed of large number of sensor nodes with limited communication and processing power. Key pre-distribution schemes using a shared large key pool have been proposed in order to overcome power and memory constraints. Establishing a secure link depends on the probability of sharing a key (secret) between two sensor nodes. In this paper, we propose a new approach for path key establishment. Our approach relies on electing trusted common nodes called ldquoproxiesrdquo that reside in an existing secure path linking the two sensor nodes. They will be used to send the generated key which will be divided into parts or nuggets according to the number of elected proxies. Our proposed approach is assessed against other algorithms. The results show that our algorithm discovers proxies faster with these proxies being located fewer hops away from both end nodes, resulting in shorter path length when compared to other existing algorithms. The results also show that our algorithm uses less transmission time than other algorithms, therefore adding efficiency by saving power.

FPGA-Based Lookup Circuit for Session-Based IP Packet Classification

In this paper, we present the architecture and implementation of an FPGA-based lookup circuit for a session-based IP packet classifier. The concept of session-based packet classification is summarized and the difference between the traditional- and session- based-classification is discussed. A preliminary hardware based architecture customised for FPGA technology is explored and its implementation using Altera Cyclone II technology is outlined. A detailed circuit analysis is presented.

A reconfigurable tag computation architecture for terabit packet scheduling

Summary form only given. We present the hardware architecture and implementation of a reconfigurable tag computation circuit for terabit packet scheduling for future QoS aware core routers. The presented implementation provides a platform for a runtime configurable scheduling architecture that is able to reallocate bandwidth on the fly. The system is implemented using FPGA technology and provides extended programmability to adapt the tag computation to a range of custom packet scheduling policies. The hardware architecture is parallel and pipelined enabling an aggregated throughput rate of 175 million tag computations per second, easily out performing current QoS router solutions. The high-level system breakdown is described and synthesis results for Altera FPGA technology are presented.

Delay-bound preservation through packet scheduling at wireless access point nodes

Wireless packet schedulers have concentrated for the most part on preserving fairness in a network environment where channels are subject to location-dependent errors. By recording the lost service and compensating flows after an error period, long-term throughput and long-term fairness can be maintained. This paper stresses that what is most pertinent to current wireless QoS however, is the preservation of delay guarantees for sessions in the face of channel errors. A traffic profile and priority based wireless fair queuing (TPP-WFQ) scheduling approach is proposed, which utilizes all available residue bandwidth in the system to allow sessions to catch up to their error-free service as quickly as possible. In addition, a bandwidth management platform that adjusts session weights for use by the scheduler is presented. Priority is given to real-time traffic with strict delay bounds for both bandwidth utilization and compensation. Simulated results illustrate how maintaining short-term delay guarantees in this way does not affect long term fairness and throughput guarantees for other sessions more tolerant to delay.